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<h1><a name="Message">Timing Messages</a></h1>
<table class="summary_table">
<tr>
<td class="label">Report Title</td>
<td>Timing Analysis Report</td>
</tr>
<tr>
<td class="label">Design File</td>
<td>F:\work\BaiduNetdiskWorkspace\verilog_Code\pmod_digitalTube-2bit\impl\gwsynthesis\pmod_digitalTube-2bit.vg</td>
</tr>
<tr>
<td class="label">Physical Constraints File</td>
<td>F:\work\BaiduNetdiskWorkspace\verilog_Code\pmod_digitalTube-2bit\src\pmod_digitalTube-2bit.cst</td>
</tr>
<tr>
<td class="label">Timing Constraint File</td>
<td>---</td>
</tr>
<tr>
<td class="label">Version</td>
<td>V1.9.9 Beta-5</td>
</tr>
<tr>
<td class="label">Part Number</td>
<td>GW5A-LV25MG121NES</td>
</tr>
<tr>
<td class="label">Device</td>
<td>GW5A-25</td>
</tr>
<tr>
<td class="label">Device Version</td>
<td>A</td>
</tr>
<tr>
<td class="label">Created Time</td>
<td>Tue Oct 31 21:09:36 2023
</td>
</tr>
<tr>
<td class="label">Legal Announcement</td>
<td>Copyright (C)2014-2023 Gowin Semiconductor Corporation. All rights reserved.</td>
</tr>
</table>
<h1><a name="Summary">Timing Summaries</a></h1>
<h2><a name="STA_Tool_Run_Summary">STA Tool Run Summary:</a></h2>
<table class="summary_table">
<tr>
<td class="label">Setup Delay Model</td>
<td>Slow 0.85V -40C ES</td>
</tr>
<tr>
<td class="label">Hold Delay Model</td>
<td>Fast 0.95V 100C ES</td>
</tr>
<tr>
<td class="label">Numbers of Paths Analyzed</td>
<td>587</td>
</tr>
<tr>
<td class="label">Numbers of Endpoints Analyzed</td>
<td>628</td>
</tr>
<tr>
<td class="label">Numbers of Falling Endpoints</td>
<td>0</td>
</tr>
<tr>
<td class="label">Numbers of Setup Violated Endpoints</td>
<td>0</td>
</tr>
<tr>
<td class="label">Numbers of Hold Violated Endpoints</td>
<td>0</td>
</tr>
</table>
<h2><a name="Clock_Report">Clock Summary:</a></h2>
<table class="detail_table">
<tr>
<th class="label">Clock Name</th>
<th class="label">Type</th>
<th class="label">Period</th>
<th class="label">Frequency(MHz)</th>
<th class="label">Rise</th>
<th class="label">Fall</th>
<th class="label">Source</th>
<th class="label">Master</th>
<th class="label">Objects</th>
</tr>
<tr>
<td>i_clk</td>
<td>Base</td>
<td>10.000</td>
<td>100.000
<td>0.000</td>
<td>5.000</td>
<td></td>
<td></td>
<td>i_clk_ibuf/I </td>
</tr>
</table>
<h2><a name="Max_Frequency_Report">Max Frequency Summary:</a></h2>
<table>
<tr>
<th>NO.</th>
<th>Clock Name</th>
<th>Constraint</th>
<th>Actual Fmax</th>
<th>Logic Level</th>
<th>Entity</th>
</tr>
<tr>
<td>1</td>
<td>i_clk</td>
<td>100.000(MHz)</td>
<td>191.663(MHz)</td>
<td>5</td>
<td>TOP</td>
</tr>
</table>
<h2><a name="Total_Negative_Slack_Report">Total Negative Slack Summary:</a></h2>
<table class="detail_table">
<tr>
<th class="label">Clock Name</th>
<th class="label">Analysis Type</th>
<th class="label">Endpoints TNS</th>
<th class="label">Number of Endpoints</th>
</tr>
<tr>
<td>i_clk</td>
<td>Setup</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>i_clk</td>
<td>Hold</td>
<td>0.000</td>
<td>0</td>
</tr>
</table>
<h1><a name="Detail">Timing Details</a></h1>
<h2><a name="All_Path_Slack_Table">Path Slacks Table:</a></h2>
<h3><a name="Setup_Slack_Table">Setup Paths Table</a></h3>
<h4>Report Command:report_timing -setup -max_paths 25 -max_common_paths 1</h4>
<table class="detail_table">
<tr>
<th class="label">Path Number</th>
<th class="label">Path Slack</th>
<th class="label">From Node</th>
<th class="label">To Node</th>
<th class="label">From Clock</th>
<th class="label">To Clock</th>
<th class="label">Relation</th>
<th class="label">Clock Skew</th>
<th class="label">Data Delay</th>
</tr>
<tr>
<td>1</td>
<td>4.782</td>
<td>button3/r_cnt_2_s0/Q</td>
<td>button3/r_cnt_11_s0/D</td>
<td>i_clk:[R]</td>
<td>i_clk:[R]</td>
<td>10.000</td>
<td>-0.025</td>
<td>5.179</td>
</tr>
<tr>
<td>2</td>
<td>4.782</td>
<td>button3/r_cnt_2_s0/Q</td>
<td>button3/r_cnt_12_s0/D</td>
<td>i_clk:[R]</td>
<td>i_clk:[R]</td>
<td>10.000</td>
<td>-0.025</td>
<td>5.179</td>
</tr>
<tr>
<td>3</td>
<td>4.894</td>
<td>digitaltube/r_cnt_21_s0/Q</td>
<td>digitaltube/r_digitalTubeOnes_0_s0/CE</td>
<td>i_clk:[R]</td>
<td>i_clk:[R]</td>
<td>10.000</td>
<td>0.032</td>
<td>4.763</td>
</tr>
<tr>
<td>4</td>
<td>4.894</td>
<td>digitaltube/r_cnt_21_s0/Q</td>
<td>digitaltube/r_digitalTubeOnes_1_s0/CE</td>
<td>i_clk:[R]</td>
<td>i_clk:[R]</td>
<td>10.000</td>
<td>0.032</td>
<td>4.763</td>
</tr>
<tr>
<td>5</td>
<td>4.894</td>
<td>digitaltube/r_cnt_21_s0/Q</td>
<td>digitaltube/r_digitalTubeOnes_2_s0/CE</td>
<td>i_clk:[R]</td>
<td>i_clk:[R]</td>
<td>10.000</td>
<td>0.032</td>
<td>4.763</td>
</tr>
<tr>
<td>6</td>
<td>4.894</td>
<td>digitaltube/r_cnt_21_s0/Q</td>
<td>digitaltube/r_digitalTubeOnes_3_s0/CE</td>
<td>i_clk:[R]</td>
<td>i_clk:[R]</td>
<td>10.000</td>
<td>0.032</td>
<td>4.763</td>
</tr>
<tr>
<td>7</td>
<td>4.973</td>
<td>digitaltube/r_cnt_21_s0/Q</td>
<td>digitaltube/r_addBuffer_3_s1/CE</td>
<td>i_clk:[R]</td>
<td>i_clk:[R]</td>
<td>10.000</td>
<td>0.034</td>
<td>4.683</td>
</tr>
<tr>
<td>8</td>
<td>4.974</td>
<td>button3/r_cnt_2_s0/Q</td>
<td>button3/r_state_s1/CE</td>
<td>i_clk:[R]</td>
<td>i_clk:[R]</td>
<td>10.000</td>
<td>0.002</td>
<td>4.713</td>
</tr>
<tr>
<td>9</td>
<td>5.019</td>
<td>digitaltube/r_cnt_21_s0/Q</td>
<td>digitaltube/r_digitalTubeTens_2_s0/CE</td>
<td>i_clk:[R]</td>
<td>i_clk:[R]</td>
<td>10.000</td>
<td>0.032</td>
<td>4.638</td>
</tr>
<tr>
<td>10</td>
<td>5.096</td>
<td>digitaltube/r_cnt_21_s0/Q</td>
<td>digitaltube/r_digitalTubeOnes_6_s0/CE</td>
<td>i_clk:[R]</td>
<td>i_clk:[R]</td>
<td>10.000</td>
<td>0.022</td>
<td>4.570</td>
</tr>
<tr>
<td>11</td>
<td>5.198</td>
<td>digitaltube/r_cnt_21_s0/Q</td>
<td>digitaltube/r_digitalTubeTens_5_s0/CE</td>
<td>i_clk:[R]</td>
<td>i_clk:[R]</td>
<td>10.000</td>
<td>0.043</td>
<td>4.448</td>
</tr>
<tr>
<td>12</td>
<td>5.208</td>
<td>digitaltube/r_cnt_21_s0/Q</td>
<td>digitaltube/r_digitalTubeTens_6_s0/CE</td>
<td>i_clk:[R]</td>
<td>i_clk:[R]</td>
<td>10.000</td>
<td>0.034</td>
<td>4.448</td>
</tr>
<tr>
<td>13</td>
<td>5.217</td>
<td>digitaltube/r_cnt_21_s0/Q</td>
<td>digitaltube/r_digitalTubeTens_4_s0/CE</td>
<td>i_clk:[R]</td>
<td>i_clk:[R]</td>
<td>10.000</td>
<td>0.024</td>
<td>4.448</td>
</tr>
<tr>
<td>14</td>
<td>5.265</td>
<td>digitaltube/r_cnt_21_s0/Q</td>
<td>digitaltube/r_addBuffer_0_s1/D</td>
<td>i_clk:[R]</td>
<td>i_clk:[R]</td>
<td>10.000</td>
<td>-0.002</td>
<td>4.674</td>
</tr>
<tr>
<td>15</td>
<td>5.296</td>
<td>digitaltube/r_addBuffer_1_s1/Q</td>
<td>digitaltube/r_cntTens_2_s1/CE</td>
<td>i_clk:[R]</td>
<td>i_clk:[R]</td>
<td>10.000</td>
<td>0.044</td>
<td>4.349</td>
</tr>
<tr>
<td>16</td>
<td>5.376</td>
<td>digitaltube/r_cnt_21_s0/Q</td>
<td>digitaltube/r_digitalTubeTens_3_s0/CE</td>
<td>i_clk:[R]</td>
<td>i_clk:[R]</td>
<td>10.000</td>
<td>0.022</td>
<td>4.290</td>
</tr>
<tr>
<td>17</td>
<td>5.397</td>
<td>digitaltube/r_cnt_21_s0/Q</td>
<td>digitaltube/r_addBuffer_1_s1/D</td>
<td>i_clk:[R]</td>
<td>i_clk:[R]</td>
<td>10.000</td>
<td>-0.002</td>
<td>4.541</td>
</tr>
<tr>
<td>18</td>
<td>5.415</td>
<td>led/r_cnt_11_s0/Q</td>
<td>led/r_cnt_0_s0/D</td>
<td>i_clk:[R]</td>
<td>i_clk:[R]</td>
<td>10.000</td>
<td>0.000</td>
<td>4.521</td>
</tr>
<tr>
<td>19</td>
<td>5.437</td>
<td>led/r_cnt_11_s0/Q</td>
<td>led/r_cnt_12_s0/D</td>
<td>i_clk:[R]</td>
<td>i_clk:[R]</td>
<td>10.000</td>
<td>-0.009</td>
<td>4.509</td>
</tr>
<tr>
<td>20</td>
<td>5.445</td>
<td>digitaltube/r_cnt_21_s0/Q</td>
<td>digitaltube/r_cnt_8_s0/D</td>
<td>i_clk:[R]</td>
<td>i_clk:[R]</td>
<td>10.000</td>
<td>-0.002</td>
<td>4.494</td>
</tr>
<tr>
<td>21</td>
<td>5.449</td>
<td>digitaltube/r_cnt_21_s0/Q</td>
<td>digitaltube/r_cnt_9_s0/D</td>
<td>i_clk:[R]</td>
<td>i_clk:[R]</td>
<td>10.000</td>
<td>-0.007</td>
<td>4.494</td>
</tr>
<tr>
<td>22</td>
<td>5.466</td>
<td>led/r_cnt_11_s0/Q</td>
<td>led/r_cnt_7_s0/D</td>
<td>i_clk:[R]</td>
<td>i_clk:[R]</td>
<td>10.000</td>
<td>-0.009</td>
<td>4.480</td>
</tr>
<tr>
<td>23</td>
<td>5.494</td>
<td>digitaltube/r_addBuffer_1_s1/Q</td>
<td>digitaltube/r_cntTens_0_s1/CE</td>
<td>i_clk:[R]</td>
<td>i_clk:[R]</td>
<td>10.000</td>
<td>0.036</td>
<td>4.159</td>
</tr>
<tr>
<td>24</td>
<td>5.494</td>
<td>digitaltube/r_addBuffer_1_s1/Q</td>
<td>digitaltube/r_cntTens_4_s1/CE</td>
<td>i_clk:[R]</td>
<td>i_clk:[R]</td>
<td>10.000</td>
<td>0.036</td>
<td>4.159</td>
</tr>
<tr>
<td>25</td>
<td>5.499</td>
<td>button3/r_cnt_2_s0/Q</td>
<td>button3/r_cnt_16_s0/D</td>
<td>i_clk:[R]</td>
<td>i_clk:[R]</td>
<td>10.000</td>
<td>0.011</td>
<td>4.426</td>
</tr>
</table>
<h3><a name="Hold_Slack_Table">Hold Paths Table</a></h3>
<h4>Report Command:report_timing -hold -max_paths 25 -max_common_paths 1</h4>
<table class="detail_table">
<tr>
<th class="label">Path Number</th>
<th class="label">Path Slack</th>
<th class="label">From Node</th>
<th class="label">To Node</th>
<th class="label">From Clock</th>
<th class="label">To Clock</th>
<th class="label">Relation</th>
<th class="label">Clock Skew</th>
<th class="label">Data Delay</th>
</tr>
<tr>
<td>1</td>
<td>0.374</td>
<td>led/r_cnt_13_s0/Q</td>
<td>led/r_cnt_13_s0/D</td>
<td>i_clk:[R]</td>
<td>i_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.375</td>
</tr>
<tr>
<td>2</td>
<td>0.374</td>
<td>led/r_cnt_25_s0/Q</td>
<td>led/r_cnt_25_s0/D</td>
<td>i_clk:[R]</td>
<td>i_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.375</td>
</tr>
<tr>
<td>3</td>
<td>0.374</td>
<td>digitaltube/ro_sel_s2/Q</td>
<td>digitaltube/ro_sel_s2/D</td>
<td>i_clk:[R]</td>
<td>i_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.375</td>
</tr>
<tr>
<td>4</td>
<td>0.374</td>
<td>digitaltube/r_cnt_6_s0/Q</td>
<td>digitaltube/r_cnt_6_s0/D</td>
<td>i_clk:[R]</td>
<td>i_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.375</td>
</tr>
<tr>
<td>5</td>
<td>0.374</td>
<td>digitaltube/r_cnt_9_s0/Q</td>
<td>digitaltube/r_cnt_9_s0/D</td>
<td>i_clk:[R]</td>
<td>i_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.375</td>
</tr>
<tr>
<td>6</td>
<td>0.374</td>
<td>digitaltube/r_cnt_10_s0/Q</td>
<td>digitaltube/r_cnt_10_s0/D</td>
<td>i_clk:[R]</td>
<td>i_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.375</td>
</tr>
<tr>
<td>7</td>
<td>0.374</td>
<td>digitaltube/r_cnt_13_s0/Q</td>
<td>digitaltube/r_cnt_13_s0/D</td>
<td>i_clk:[R]</td>
<td>i_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.375</td>
</tr>
<tr>
<td>8</td>
<td>0.374</td>
<td>digitaltube/r_cnt_14_s0/Q</td>
<td>digitaltube/r_cnt_14_s0/D</td>
<td>i_clk:[R]</td>
<td>i_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.375</td>
</tr>
<tr>
<td>9</td>
<td>0.374</td>
<td>digitaltube/r_cnt_18_s0/Q</td>
<td>digitaltube/r_cnt_18_s0/D</td>
<td>i_clk:[R]</td>
<td>i_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.375</td>
</tr>
<tr>
<td>10</td>
<td>0.374</td>
<td>button3/r_cnt_2_s0/Q</td>
<td>button3/r_cnt_2_s0/D</td>
<td>i_clk:[R]</td>
<td>i_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.375</td>
</tr>
<tr>
<td>11</td>
<td>0.374</td>
<td>button3/r_cnt_3_s0/Q</td>
<td>button3/r_cnt_3_s0/D</td>
<td>i_clk:[R]</td>
<td>i_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.375</td>
</tr>
<tr>
<td>12</td>
<td>0.374</td>
<td>button3/r_cnt_5_s0/Q</td>
<td>button3/r_cnt_5_s0/D</td>
<td>i_clk:[R]</td>
<td>i_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.375</td>
</tr>
<tr>
<td>13</td>
<td>0.374</td>
<td>button2/r_cnt_23_s0/Q</td>
<td>button2/r_cnt_23_s0/D</td>
<td>i_clk:[R]</td>
<td>i_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.375</td>
</tr>
<tr>
<td>14</td>
<td>0.374</td>
<td>button2/r_cnt_2_s0/Q</td>
<td>button2/r_cnt_2_s0/D</td>
<td>i_clk:[R]</td>
<td>i_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.375</td>
</tr>
<tr>
<td>15</td>
<td>0.374</td>
<td>button2/r_cnt_5_s0/Q</td>
<td>button2/r_cnt_5_s0/D</td>
<td>i_clk:[R]</td>
<td>i_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.375</td>
</tr>
<tr>
<td>16</td>
<td>0.374</td>
<td>button2/r_cnt_9_s0/Q</td>
<td>button2/r_cnt_9_s0/D</td>
<td>i_clk:[R]</td>
<td>i_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.375</td>
</tr>
<tr>
<td>17</td>
<td>0.374</td>
<td>button1/r_cnt_3_s0/Q</td>
<td>button1/r_cnt_3_s0/D</td>
<td>i_clk:[R]</td>
<td>i_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.375</td>
</tr>
<tr>
<td>18</td>
<td>0.374</td>
<td>button1/r_cnt_6_s0/Q</td>
<td>button1/r_cnt_6_s0/D</td>
<td>i_clk:[R]</td>
<td>i_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.375</td>
</tr>
<tr>
<td>19</td>
<td>0.374</td>
<td>button1/r_cnt_15_s0/Q</td>
<td>button1/r_cnt_15_s0/D</td>
<td>i_clk:[R]</td>
<td>i_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.375</td>
</tr>
<tr>
<td>20</td>
<td>0.374</td>
<td>button1/r_cnt_17_s0/Q</td>
<td>button1/r_cnt_17_s0/D</td>
<td>i_clk:[R]</td>
<td>i_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.375</td>
</tr>
<tr>
<td>21</td>
<td>0.374</td>
<td>button0/r_cnt_2_s0/Q</td>
<td>button0/r_cnt_2_s0/D</td>
<td>i_clk:[R]</td>
<td>i_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.375</td>
</tr>
<tr>
<td>22</td>
<td>0.374</td>
<td>button0/r_cnt_6_s0/Q</td>
<td>button0/r_cnt_6_s0/D</td>
<td>i_clk:[R]</td>
<td>i_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.375</td>
</tr>
<tr>
<td>23</td>
<td>0.374</td>
<td>button0/r_cnt_9_s0/Q</td>
<td>button0/r_cnt_9_s0/D</td>
<td>i_clk:[R]</td>
<td>i_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.375</td>
</tr>
<tr>
<td>24</td>
<td>0.374</td>
<td>button0/r_cnt_13_s0/Q</td>
<td>button0/r_cnt_13_s0/D</td>
<td>i_clk:[R]</td>
<td>i_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.375</td>
</tr>
<tr>
<td>25</td>
<td>0.374</td>
<td>button0/r_cnt_21_s0/Q</td>
<td>button0/r_cnt_21_s0/D</td>
<td>i_clk:[R]</td>
<td>i_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.375</td>
</tr>
</table>
<h3><a name="Recovery_Slack_Table">Recovery Paths Table</a></h3>
<h4>Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1</h4>
<h4>Nothing to report!</h4>
<h3><a name="Removal_Slack_Table">Removal Paths Table</a></h3>
<h4>Report Command:report_timing -removal -max_paths 25 -max_common_paths 1</h4>
<h4>Nothing to report!</h4>
<h2><a name="MIN_PULSE_WIDTH_TABLE">Minimum Pulse Width Table:</a></h2>
<table class="detail_table">
<tr>
<th class="label">Number</th>
<th class="label">Slack</th>
<th class="label">Actual Width</th>
<th class="label">Required Width</th>
<th class="label">Type</th>
<th class="label">Clock</th>
<th class="label">Objects</th>
</tr>
<h4>Report Command:report_min_pulse_width -nworst 10 -detail</h4>
<tr>
<td>1</td>
<td>4.231</td>
<td>4.481</td>
<td>0.250</td>
<td>Low Pulse Width</td>
<td>i_clk</td>
<td>button3/r_cnt_13_s0</td>
</tr>
<tr>
<td>2</td>
<td>4.231</td>
<td>4.481</td>
<td>0.250</td>
<td>Low Pulse Width</td>
<td>i_clk</td>
<td>digitaltube/r_cnt_11_s0</td>
</tr>
<tr>
<td>3</td>
<td>4.231</td>
<td>4.481</td>
<td>0.250</td>
<td>Low Pulse Width</td>
<td>i_clk</td>
<td>digitaltube/r_cnt_0_s0</td>
</tr>
<tr>
<td>4</td>
<td>4.231</td>
<td>4.481</td>
<td>0.250</td>
<td>Low Pulse Width</td>
<td>i_clk</td>
<td>led/r_cnt_21_s0</td>
</tr>
<tr>
<td>5</td>
<td>4.231</td>
<td>4.481</td>
<td>0.250</td>
<td>Low Pulse Width</td>
<td>i_clk</td>
<td>led/r_cnt_19_s0</td>
</tr>
<tr>
<td>6</td>
<td>4.232</td>
<td>4.482</td>
<td>0.250</td>
<td>Low Pulse Width</td>
<td>i_clk</td>
<td>digitaltube/r_cnt_19_s0</td>
</tr>
<tr>
<td>7</td>
<td>4.232</td>
<td>4.482</td>
<td>0.250</td>
<td>Low Pulse Width</td>
<td>i_clk</td>
<td>digitaltube/r_cnt_17_s0</td>
</tr>
<tr>
<td>8</td>
<td>4.232</td>
<td>4.482</td>
<td>0.250</td>
<td>Low Pulse Width</td>
<td>i_clk</td>
<td>digitaltube/r_cnt_12_s0</td>
</tr>
<tr>
<td>9</td>
<td>4.232</td>
<td>4.482</td>
<td>0.250</td>
<td>Low Pulse Width</td>
<td>i_clk</td>
<td>button3/r_cnt_7_s0</td>
</tr>
<tr>
<td>10</td>
<td>4.232</td>
<td>4.482</td>
<td>0.250</td>
<td>Low Pulse Width</td>
<td>i_clk</td>
<td>button3/r_cnt_6_s0</td>
</tr>
</table>
<h2><a name="Timing_Report_by_Analysis_Type">Timing Report By Analysis Type:</a></h2>
<h3><a name="Setup_Analysis">Setup Analysis Report</a></h3>
<h4>Report Command:report_timing -setup -max_paths 25 -max_common_paths 1</h4>
<h3>Path1</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>4.782</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>6.739</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>11.522</td>
</tr>
<tr>
<td class="label">From</td>
<td>button3/r_cnt_2_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>button3/r_cnt_11_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>i_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>i_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>i_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>i_clk_ibuf/I</td>
</tr>
<tr>
<td>0.683</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>204</td>
<td>IOB12[A]</td>
<td>i_clk_ibuf/O</td>
</tr>
<tr>
<td>1.561</td>
<td>0.878</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C41[1][A]</td>
<td>button3/r_cnt_2_s0/CLK</td>
</tr>
<tr>
<td>1.943</td>
<td>0.382</td>
<td>tC2Q</td>
<td>RR</td>
<td>3</td>
<td>R18C41[1][A]</td>
<td style=" font-weight:bold;">button3/r_cnt_2_s0/Q</td>
</tr>
<tr>
<td>2.836</td>
<td>0.893</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C40[3][A]</td>
<td>button3/n89_s3/I2</td>
</tr>
<tr>
<td>3.251</td>
<td>0.415</td>
<td>tINS</td>
<td>RR</td>
<td>4</td>
<td>R20C40[3][A]</td>
<td style=" background: #97FFFF;">button3/n89_s3/F</td>
</tr>
<tr>
<td>3.411</td>
<td>0.160</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C41[2][A]</td>
<td>button3/n85_s3/I2</td>
</tr>
<tr>
<td>3.927</td>
<td>0.516</td>
<td>tINS</td>
<td>RR</td>
<td>6</td>
<td>R20C41[2][A]</td>
<td style=" background: #97FFFF;">button3/n85_s3/F</td>
</tr>
<tr>
<td>4.807</td>
<td>0.880</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C41[0][A]</td>
<td>button3/n82_s4/I3</td>
</tr>
<tr>
<td>5.323</td>
<td>0.516</td>
<td>tINS</td>
<td>RR</td>
<td>2</td>
<td>R17C41[0][A]</td>
<td style=" background: #97FFFF;">button3/n82_s4/F</td>
</tr>
<tr>
<td>6.213</td>
<td>0.890</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C40[0][A]</td>
<td>button3/n82_s2/I2</td>
</tr>
<tr>
<td>6.739</td>
<td>0.526</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R20C40[0][A]</td>
<td style=" background: #97FFFF;">button3/n82_s2/F</td>
</tr>
<tr>
<td>6.739</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C40[0][A]</td>
<td style=" font-weight:bold;">button3/r_cnt_11_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>i_clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>i_clk_ibuf/I</td>
</tr>
<tr>
<td>10.682</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>204</td>
<td>IOB12[A]</td>
<td>i_clk_ibuf/O</td>
</tr>
<tr>
<td>11.586</td>
<td>0.903</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C40[0][A]</td>
<td>button3/r_cnt_11_s0/CLK</td>
</tr>
<tr>
<td>11.522</td>
<td>-0.064</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R20C40[0][A]</td>
<td>button3/r_cnt_11_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.025</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>5</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.683, 43.732%; route: 0.878, 56.268%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 1.974, 38.112%; route: 2.822, 54.502%; tC2Q: 0.382, 7.386%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.683, 43.043%; route: 0.903, 56.957%</td>
</tr>
</table>
<h3>Path2</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>4.782</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>6.739</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>11.522</td>
</tr>
<tr>
<td class="label">From</td>
<td>button3/r_cnt_2_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>button3/r_cnt_12_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>i_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>i_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>i_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>i_clk_ibuf/I</td>
</tr>
<tr>
<td>0.683</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>204</td>
<td>IOB12[A]</td>
<td>i_clk_ibuf/O</td>
</tr>
<tr>
<td>1.561</td>
<td>0.878</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C41[1][A]</td>
<td>button3/r_cnt_2_s0/CLK</td>
</tr>
<tr>
<td>1.943</td>
<td>0.382</td>
<td>tC2Q</td>
<td>RR</td>
<td>3</td>
<td>R18C41[1][A]</td>
<td style=" font-weight:bold;">button3/r_cnt_2_s0/Q</td>
</tr>
<tr>
<td>2.836</td>
<td>0.893</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C40[3][A]</td>
<td>button3/n89_s3/I2</td>
</tr>
<tr>
<td>3.251</td>
<td>0.415</td>
<td>tINS</td>
<td>RR</td>
<td>4</td>
<td>R20C40[3][A]</td>
<td style=" background: #97FFFF;">button3/n89_s3/F</td>
</tr>
<tr>
<td>3.411</td>
<td>0.160</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C41[2][A]</td>
<td>button3/n85_s3/I2</td>
</tr>
<tr>
<td>3.927</td>
<td>0.516</td>
<td>tINS</td>
<td>RR</td>
<td>6</td>
<td>R20C41[2][A]</td>
<td style=" background: #97FFFF;">button3/n85_s3/F</td>
</tr>
<tr>
<td>4.807</td>
<td>0.880</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C41[0][A]</td>
<td>button3/n82_s4/I3</td>
</tr>
<tr>
<td>5.323</td>
<td>0.516</td>
<td>tINS</td>
<td>RR</td>
<td>2</td>
<td>R17C41[0][A]</td>
<td style=" background: #97FFFF;">button3/n82_s4/F</td>
</tr>
<tr>
<td>6.213</td>
<td>0.890</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C40[0][B]</td>
<td>button3/n81_s2/I1</td>
</tr>
<tr>
<td>6.739</td>
<td>0.526</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R20C40[0][B]</td>
<td style=" background: #97FFFF;">button3/n81_s2/F</td>
</tr>
<tr>
<td>6.739</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C40[0][B]</td>
<td style=" font-weight:bold;">button3/r_cnt_12_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>i_clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>i_clk_ibuf/I</td>
</tr>
<tr>
<td>10.682</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>204</td>
<td>IOB12[A]</td>
<td>i_clk_ibuf/O</td>
</tr>
<tr>
<td>11.586</td>
<td>0.903</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C40[0][B]</td>
<td>button3/r_cnt_12_s0/CLK</td>
</tr>
<tr>
<td>11.522</td>
<td>-0.064</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R20C40[0][B]</td>
<td>button3/r_cnt_12_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.025</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>5</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.683, 43.732%; route: 0.878, 56.268%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 1.974, 38.112%; route: 2.822, 54.502%; tC2Q: 0.382, 7.386%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.683, 43.043%; route: 0.903, 56.957%</td>
</tr>
</table>
<h3>Path3</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>4.894</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>6.346</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>11.240</td>
</tr>
<tr>
<td class="label">From</td>
<td>digitaltube/r_cnt_21_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>digitaltube/r_digitalTubeOnes_0_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>i_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>i_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>i_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>i_clk_ibuf/I</td>
</tr>
<tr>
<td>0.683</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>204</td>
<td>IOB12[A]</td>
<td>i_clk_ibuf/O</td>
</tr>
<tr>
<td>1.583</td>
<td>0.901</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C34[3][A]</td>
<td>digitaltube/r_cnt_21_s0/CLK</td>
</tr>
<tr>
<td>1.966</td>
<td>0.382</td>
<td>tC2Q</td>
<td>RR</td>
<td>3</td>
<td>R21C34[3][A]</td>
<td style=" font-weight:bold;">digitaltube/r_cnt_21_s0/Q</td>
</tr>
<tr>
<td>2.379</td>
<td>0.414</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C34[2][A]</td>
<td>digitaltube/n29_s6/I1</td>
</tr>
<tr>
<td>2.841</td>
<td>0.461</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R20C34[2][A]</td>
<td style=" background: #97FFFF;">digitaltube/n29_s6/F</td>
</tr>
<tr>
<td>2.998</td>
<td>0.157</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C33[1][B]</td>
<td>digitaltube/n29_s2/I2</td>
</tr>
<tr>
<td>3.514</td>
<td>0.516</td>
<td>tINS</td>
<td>RR</td>
<td>5</td>
<td>R20C33[1][B]</td>
<td style=" background: #97FFFF;">digitaltube/n29_s2/F</td>
</tr>
<tr>
<td>3.677</td>
<td>0.162</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C32[2][A]</td>
<td>digitaltube/r_cntOnes_4_s3/I1</td>
</tr>
<tr>
<td>4.138</td>
<td>0.461</td>
<td>tINS</td>
<td>RR</td>
<td>25</td>
<td>R20C32[2][A]</td>
<td style=" background: #97FFFF;">digitaltube/r_cntOnes_4_s3/F</td>
</tr>
<tr>
<td>5.074</td>
<td>0.936</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C33[3][A]</td>
<td>digitaltube/r_digitalTubeOnes_6_s2/I3</td>
</tr>
<tr>
<td>5.339</td>
<td>0.265</td>
<td>tINS</td>
<td>RR</td>
<td>7</td>
<td>R18C33[3][A]</td>
<td style=" background: #97FFFF;">digitaltube/r_digitalTubeOnes_6_s2/F</td>
</tr>
<tr>
<td>6.346</td>
<td>1.006</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C34[0][A]</td>
<td style=" font-weight:bold;">digitaltube/r_digitalTubeOnes_0_s0/CE</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>i_clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>i_clk_ibuf/I</td>
</tr>
<tr>
<td>10.682</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>204</td>
<td>IOB12[A]</td>
<td>i_clk_ibuf/O</td>
</tr>
<tr>
<td>11.551</td>
<td>0.869</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C34[0][A]</td>
<td>digitaltube/r_digitalTubeOnes_0_s0/CLK</td>
</tr>
<tr>
<td>11.240</td>
<td>-0.311</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R18C34[0][A]</td>
<td>digitaltube/r_digitalTubeOnes_0_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.032</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>5</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.683, 43.111%; route: 0.901, 56.889%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 1.704, 35.774%; route: 2.676, 56.194%; tC2Q: 0.382, 8.031%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.683, 43.997%; route: 0.869, 56.003%</td>
</tr>
</table>
<h3>Path4</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>4.894</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>6.346</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>11.240</td>
</tr>
<tr>
<td class="label">From</td>
<td>digitaltube/r_cnt_21_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>digitaltube/r_digitalTubeOnes_1_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>i_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>i_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>i_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>i_clk_ibuf/I</td>
</tr>
<tr>
<td>0.683</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>204</td>
<td>IOB12[A]</td>
<td>i_clk_ibuf/O</td>
</tr>
<tr>
<td>1.583</td>
<td>0.901</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C34[3][A]</td>
<td>digitaltube/r_cnt_21_s0/CLK</td>
</tr>
<tr>
<td>1.966</td>
<td>0.382</td>
<td>tC2Q</td>
<td>RR</td>
<td>3</td>
<td>R21C34[3][A]</td>
<td style=" font-weight:bold;">digitaltube/r_cnt_21_s0/Q</td>
</tr>
<tr>
<td>2.379</td>
<td>0.414</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C34[2][A]</td>
<td>digitaltube/n29_s6/I1</td>
</tr>
<tr>
<td>2.841</td>
<td>0.461</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R20C34[2][A]</td>
<td style=" background: #97FFFF;">digitaltube/n29_s6/F</td>
</tr>
<tr>
<td>2.998</td>
<td>0.157</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C33[1][B]</td>
<td>digitaltube/n29_s2/I2</td>
</tr>
<tr>
<td>3.514</td>
<td>0.516</td>
<td>tINS</td>
<td>RR</td>
<td>5</td>
<td>R20C33[1][B]</td>
<td style=" background: #97FFFF;">digitaltube/n29_s2/F</td>
</tr>
<tr>
<td>3.677</td>
<td>0.162</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C32[2][A]</td>
<td>digitaltube/r_cntOnes_4_s3/I1</td>
</tr>
<tr>
<td>4.138</td>
<td>0.461</td>
<td>tINS</td>
<td>RR</td>
<td>25</td>
<td>R20C32[2][A]</td>
<td style=" background: #97FFFF;">digitaltube/r_cntOnes_4_s3/F</td>
</tr>
<tr>
<td>5.074</td>
<td>0.936</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C33[3][A]</td>
<td>digitaltube/r_digitalTubeOnes_6_s2/I3</td>
</tr>
<tr>
<td>5.339</td>
<td>0.265</td>
<td>tINS</td>
<td>RR</td>
<td>7</td>
<td>R18C33[3][A]</td>
<td style=" background: #97FFFF;">digitaltube/r_digitalTubeOnes_6_s2/F</td>
</tr>
<tr>
<td>6.346</td>
<td>1.006</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C34[0][B]</td>
<td style=" font-weight:bold;">digitaltube/r_digitalTubeOnes_1_s0/CE</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>i_clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>i_clk_ibuf/I</td>
</tr>
<tr>
<td>10.682</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>204</td>
<td>IOB12[A]</td>
<td>i_clk_ibuf/O</td>
</tr>
<tr>
<td>11.551</td>
<td>0.869</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C34[0][B]</td>
<td>digitaltube/r_digitalTubeOnes_1_s0/CLK</td>
</tr>
<tr>
<td>11.240</td>
<td>-0.311</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R18C34[0][B]</td>
<td>digitaltube/r_digitalTubeOnes_1_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.032</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>5</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.683, 43.111%; route: 0.901, 56.889%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 1.704, 35.774%; route: 2.676, 56.194%; tC2Q: 0.382, 8.031%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.683, 43.997%; route: 0.869, 56.003%</td>
</tr>
</table>
<h3>Path5</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>4.894</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>6.346</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>11.240</td>
</tr>
<tr>
<td class="label">From</td>
<td>digitaltube/r_cnt_21_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>digitaltube/r_digitalTubeOnes_2_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>i_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>i_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>i_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>i_clk_ibuf/I</td>
</tr>
<tr>
<td>0.683</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>204</td>
<td>IOB12[A]</td>
<td>i_clk_ibuf/O</td>
</tr>
<tr>
<td>1.583</td>
<td>0.901</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C34[3][A]</td>
<td>digitaltube/r_cnt_21_s0/CLK</td>
</tr>
<tr>
<td>1.966</td>
<td>0.382</td>
<td>tC2Q</td>
<td>RR</td>
<td>3</td>
<td>R21C34[3][A]</td>
<td style=" font-weight:bold;">digitaltube/r_cnt_21_s0/Q</td>
</tr>
<tr>
<td>2.379</td>
<td>0.414</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C34[2][A]</td>
<td>digitaltube/n29_s6/I1</td>
</tr>
<tr>
<td>2.841</td>
<td>0.461</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R20C34[2][A]</td>
<td style=" background: #97FFFF;">digitaltube/n29_s6/F</td>
</tr>
<tr>
<td>2.998</td>
<td>0.157</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C33[1][B]</td>
<td>digitaltube/n29_s2/I2</td>
</tr>
<tr>
<td>3.514</td>
<td>0.516</td>
<td>tINS</td>
<td>RR</td>
<td>5</td>
<td>R20C33[1][B]</td>
<td style=" background: #97FFFF;">digitaltube/n29_s2/F</td>
</tr>
<tr>
<td>3.677</td>
<td>0.162</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C32[2][A]</td>
<td>digitaltube/r_cntOnes_4_s3/I1</td>
</tr>
<tr>
<td>4.138</td>
<td>0.461</td>
<td>tINS</td>
<td>RR</td>
<td>25</td>
<td>R20C32[2][A]</td>
<td style=" background: #97FFFF;">digitaltube/r_cntOnes_4_s3/F</td>
</tr>
<tr>
<td>5.074</td>
<td>0.936</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C33[3][A]</td>
<td>digitaltube/r_digitalTubeOnes_6_s2/I3</td>
</tr>
<tr>
<td>5.339</td>
<td>0.265</td>
<td>tINS</td>
<td>RR</td>
<td>7</td>
<td>R18C33[3][A]</td>
<td style=" background: #97FFFF;">digitaltube/r_digitalTubeOnes_6_s2/F</td>
</tr>
<tr>
<td>6.346</td>
<td>1.006</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C34[2][A]</td>
<td style=" font-weight:bold;">digitaltube/r_digitalTubeOnes_2_s0/CE</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>i_clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>i_clk_ibuf/I</td>
</tr>
<tr>
<td>10.682</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>204</td>
<td>IOB12[A]</td>
<td>i_clk_ibuf/O</td>
</tr>
<tr>
<td>11.551</td>
<td>0.869</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C34[2][A]</td>
<td>digitaltube/r_digitalTubeOnes_2_s0/CLK</td>
</tr>
<tr>
<td>11.240</td>
<td>-0.311</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R18C34[2][A]</td>
<td>digitaltube/r_digitalTubeOnes_2_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.032</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>5</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.683, 43.111%; route: 0.901, 56.889%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 1.704, 35.774%; route: 2.676, 56.194%; tC2Q: 0.382, 8.031%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.683, 43.997%; route: 0.869, 56.003%</td>
</tr>
</table>
<h3>Path6</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>4.894</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>6.346</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>11.240</td>
</tr>
<tr>
<td class="label">From</td>
<td>digitaltube/r_cnt_21_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>digitaltube/r_digitalTubeOnes_3_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>i_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>i_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>i_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>i_clk_ibuf/I</td>
</tr>
<tr>
<td>0.683</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>204</td>
<td>IOB12[A]</td>
<td>i_clk_ibuf/O</td>
</tr>
<tr>
<td>1.583</td>
<td>0.901</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C34[3][A]</td>
<td>digitaltube/r_cnt_21_s0/CLK</td>
</tr>
<tr>
<td>1.966</td>
<td>0.382</td>
<td>tC2Q</td>
<td>RR</td>
<td>3</td>
<td>R21C34[3][A]</td>
<td style=" font-weight:bold;">digitaltube/r_cnt_21_s0/Q</td>
</tr>
<tr>
<td>2.379</td>
<td>0.414</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C34[2][A]</td>
<td>digitaltube/n29_s6/I1</td>
</tr>
<tr>
<td>2.841</td>
<td>0.461</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R20C34[2][A]</td>
<td style=" background: #97FFFF;">digitaltube/n29_s6/F</td>
</tr>
<tr>
<td>2.998</td>
<td>0.157</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C33[1][B]</td>
<td>digitaltube/n29_s2/I2</td>
</tr>
<tr>
<td>3.514</td>
<td>0.516</td>
<td>tINS</td>
<td>RR</td>
<td>5</td>
<td>R20C33[1][B]</td>
<td style=" background: #97FFFF;">digitaltube/n29_s2/F</td>
</tr>
<tr>
<td>3.677</td>
<td>0.162</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C32[2][A]</td>
<td>digitaltube/r_cntOnes_4_s3/I1</td>
</tr>
<tr>
<td>4.138</td>
<td>0.461</td>
<td>tINS</td>
<td>RR</td>
<td>25</td>
<td>R20C32[2][A]</td>
<td style=" background: #97FFFF;">digitaltube/r_cntOnes_4_s3/F</td>
</tr>
<tr>
<td>5.074</td>
<td>0.936</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C33[3][A]</td>
<td>digitaltube/r_digitalTubeOnes_6_s2/I3</td>
</tr>
<tr>
<td>5.339</td>
<td>0.265</td>
<td>tINS</td>
<td>RR</td>
<td>7</td>
<td>R18C33[3][A]</td>
<td style=" background: #97FFFF;">digitaltube/r_digitalTubeOnes_6_s2/F</td>
</tr>
<tr>
<td>6.346</td>
<td>1.006</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C34[2][B]</td>
<td style=" font-weight:bold;">digitaltube/r_digitalTubeOnes_3_s0/CE</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>i_clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>i_clk_ibuf/I</td>
</tr>
<tr>
<td>10.682</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>204</td>
<td>IOB12[A]</td>
<td>i_clk_ibuf/O</td>
</tr>
<tr>
<td>11.551</td>
<td>0.869</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C34[2][B]</td>
<td>digitaltube/r_digitalTubeOnes_3_s0/CLK</td>
</tr>
<tr>
<td>11.240</td>
<td>-0.311</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R18C34[2][B]</td>
<td>digitaltube/r_digitalTubeOnes_3_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.032</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>5</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.683, 43.111%; route: 0.901, 56.889%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 1.704, 35.774%; route: 2.676, 56.194%; tC2Q: 0.382, 8.031%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.683, 43.997%; route: 0.869, 56.003%</td>
</tr>
</table>
<h3>Path7</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>4.973</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>6.266</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>11.238</td>
</tr>
<tr>
<td class="label">From</td>
<td>digitaltube/r_cnt_21_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>digitaltube/r_addBuffer_3_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>i_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>i_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>i_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>i_clk_ibuf/I</td>
</tr>
<tr>
<td>0.683</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>204</td>
<td>IOB12[A]</td>
<td>i_clk_ibuf/O</td>
</tr>
<tr>
<td>1.583</td>
<td>0.901</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C34[3][A]</td>
<td>digitaltube/r_cnt_21_s0/CLK</td>
</tr>
<tr>
<td>1.966</td>
<td>0.382</td>
<td>tC2Q</td>
<td>RR</td>
<td>3</td>
<td>R21C34[3][A]</td>
<td style=" font-weight:bold;">digitaltube/r_cnt_21_s0/Q</td>
</tr>
<tr>
<td>2.379</td>
<td>0.414</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C34[2][A]</td>
<td>digitaltube/n29_s6/I1</td>
</tr>
<tr>
<td>2.841</td>
<td>0.461</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R20C34[2][A]</td>
<td style=" background: #97FFFF;">digitaltube/n29_s6/F</td>
</tr>
<tr>
<td>2.998</td>
<td>0.157</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C33[1][B]</td>
<td>digitaltube/n29_s2/I2</td>
</tr>
<tr>
<td>3.514</td>
<td>0.516</td>
<td>tINS</td>
<td>RR</td>
<td>5</td>
<td>R20C33[1][B]</td>
<td style=" background: #97FFFF;">digitaltube/n29_s2/F</td>
</tr>
<tr>
<td>3.677</td>
<td>0.162</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C32[2][A]</td>
<td>digitaltube/r_cntOnes_4_s3/I1</td>
</tr>
<tr>
<td>4.138</td>
<td>0.461</td>
<td>tINS</td>
<td>RR</td>
<td>25</td>
<td>R20C32[2][A]</td>
<td style=" background: #97FFFF;">digitaltube/r_cntOnes_4_s3/F</td>
</tr>
<tr>
<td>5.267</td>
<td>1.129</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C36[1][B]</td>
<td>digitaltube/r_addBuffer_3_s3/I2</td>
</tr>
<tr>
<td>5.728</td>
<td>0.461</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R17C36[1][B]</td>
<td style=" background: #97FFFF;">digitaltube/r_addBuffer_3_s3/F</td>
</tr>
<tr>
<td>6.266</td>
<td>0.537</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C32[0][A]</td>
<td style=" font-weight:bold;">digitaltube/r_addBuffer_3_s1/CE</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>i_clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>i_clk_ibuf/I</td>
</tr>
<tr>
<td>10.682</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>204</td>
<td>IOB12[A]</td>
<td>i_clk_ibuf/O</td>
</tr>
<tr>
<td>11.549</td>
<td>0.867</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C32[0][A]</td>
<td>digitaltube/r_addBuffer_3_s1/CLK</td>
</tr>
<tr>
<td>11.238</td>
<td>-0.311</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R17C32[0][A]</td>
<td>digitaltube/r_addBuffer_3_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.034</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>5</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.683, 43.111%; route: 0.901, 56.889%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 1.900, 40.577%; route: 2.400, 51.255%; tC2Q: 0.382, 8.169%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.683, 44.050%; route: 0.867, 55.950%</td>
</tr>
</table>
<h3>Path8</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>4.974</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>6.273</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>11.248</td>
</tr>
<tr>
<td class="label">From</td>
<td>button3/r_cnt_2_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>button3/r_state_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>i_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>i_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>i_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>i_clk_ibuf/I</td>
</tr>
<tr>
<td>0.683</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>204</td>
<td>IOB12[A]</td>
<td>i_clk_ibuf/O</td>
</tr>
<tr>
<td>1.561</td>
<td>0.878</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C41[1][A]</td>
<td>button3/r_cnt_2_s0/CLK</td>
</tr>
<tr>
<td>1.943</td>
<td>0.382</td>
<td>tC2Q</td>
<td>RR</td>
<td>3</td>
<td>R18C41[1][A]</td>
<td style=" font-weight:bold;">button3/r_cnt_2_s0/Q</td>
</tr>
<tr>
<td>2.836</td>
<td>0.893</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C40[3][A]</td>
<td>button3/n89_s3/I2</td>
</tr>
<tr>
<td>3.251</td>
<td>0.415</td>
<td>tINS</td>
<td>RR</td>
<td>4</td>
<td>R20C40[3][A]</td>
<td style=" background: #97FFFF;">button3/n89_s3/F</td>
</tr>
<tr>
<td>3.954</td>
<td>0.704</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C41[0][B]</td>
<td>button3/r_state_s12/I0</td>
</tr>
<tr>
<td>4.481</td>
<td>0.526</td>
<td>tINS</td>
<td>RR</td>
<td>3</td>
<td>R18C41[0][B]</td>
<td style=" background: #97FFFF;">button3/r_state_s12/F</td>
</tr>
<tr>
<td>5.024</td>
<td>0.544</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C41[0][A]</td>
<td>button3/r_state_s3/I0</td>
</tr>
<tr>
<td>5.541</td>
<td>0.516</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R20C41[0][A]</td>
<td style=" background: #97FFFF;">button3/r_state_s3/F</td>
</tr>
<tr>
<td>6.273</td>
<td>0.733</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C41[2][B]</td>
<td style=" font-weight:bold;">button3/r_state_s1/CE</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>i_clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>i_clk_ibuf/I</td>
</tr>
<tr>
<td>10.682</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>204</td>
<td>IOB12[A]</td>
<td>i_clk_ibuf/O</td>
</tr>
<tr>
<td>11.559</td>
<td>0.876</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C41[2][B]</td>
<td>button3/r_state_s1/CLK</td>
</tr>
<tr>
<td>11.248</td>
<td>-0.311</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R17C41[2][B]</td>
<td>button3/r_state_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.002</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>4</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.683, 43.732%; route: 0.878, 56.268%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 1.457, 30.928%; route: 2.873, 60.955%; tC2Q: 0.382, 8.117%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.683, 43.785%; route: 0.876, 56.215%</td>
</tr>
</table>
<h3>Path9</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>5.019</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>6.221</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>11.240</td>
</tr>
<tr>
<td class="label">From</td>
<td>digitaltube/r_cnt_21_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>digitaltube/r_digitalTubeTens_2_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>i_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>i_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>i_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>i_clk_ibuf/I</td>
</tr>
<tr>
<td>0.683</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>204</td>
<td>IOB12[A]</td>
<td>i_clk_ibuf/O</td>
</tr>
<tr>
<td>1.583</td>
<td>0.901</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C34[3][A]</td>
<td>digitaltube/r_cnt_21_s0/CLK</td>
</tr>
<tr>
<td>1.966</td>
<td>0.382</td>
<td>tC2Q</td>
<td>RR</td>
<td>3</td>
<td>R21C34[3][A]</td>
<td style=" font-weight:bold;">digitaltube/r_cnt_21_s0/Q</td>
</tr>
<tr>
<td>2.379</td>
<td>0.414</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C34[2][A]</td>
<td>digitaltube/n29_s6/I1</td>
</tr>
<tr>
<td>2.841</td>
<td>0.461</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R20C34[2][A]</td>
<td style=" background: #97FFFF;">digitaltube/n29_s6/F</td>
</tr>
<tr>
<td>2.998</td>
<td>0.157</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C33[1][B]</td>
<td>digitaltube/n29_s2/I2</td>
</tr>
<tr>
<td>3.514</td>
<td>0.516</td>
<td>tINS</td>
<td>RR</td>
<td>5</td>
<td>R20C33[1][B]</td>
<td style=" background: #97FFFF;">digitaltube/n29_s2/F</td>
</tr>
<tr>
<td>3.677</td>
<td>0.162</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C32[2][A]</td>
<td>digitaltube/r_cntOnes_4_s3/I1</td>
</tr>
<tr>
<td>4.138</td>
<td>0.461</td>
<td>tINS</td>
<td>RR</td>
<td>25</td>
<td>R20C32[2][A]</td>
<td style=" background: #97FFFF;">digitaltube/r_cntOnes_4_s3/F</td>
</tr>
<tr>
<td>5.077</td>
<td>0.939</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C35[1][B]</td>
<td>digitaltube/r_digitalTubeTens_6_s2/I3</td>
</tr>
<tr>
<td>5.538</td>
<td>0.461</td>
<td>tINS</td>
<td>RR</td>
<td>7</td>
<td>R18C35[1][B]</td>
<td style=" background: #97FFFF;">digitaltube/r_digitalTubeTens_6_s2/F</td>
</tr>
<tr>
<td>6.221</td>
<td>0.683</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C34[1][B]</td>
<td style=" font-weight:bold;">digitaltube/r_digitalTubeTens_2_s0/CE</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>i_clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>i_clk_ibuf/I</td>
</tr>
<tr>
<td>10.682</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>204</td>
<td>IOB12[A]</td>
<td>i_clk_ibuf/O</td>
</tr>
<tr>
<td>11.551</td>
<td>0.869</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C34[1][B]</td>
<td>digitaltube/r_digitalTubeTens_2_s0/CLK</td>
</tr>
<tr>
<td>11.240</td>
<td>-0.311</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R18C34[1][B]</td>
<td>digitaltube/r_digitalTubeTens_2_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.032</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>5</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.683, 43.111%; route: 0.901, 56.889%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 1.900, 40.970%; route: 2.355, 50.782%; tC2Q: 0.382, 8.248%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.683, 43.997%; route: 0.869, 56.003%</td>
</tr>
</table>
<h3>Path10</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>5.096</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>6.153</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>11.249</td>
</tr>
<tr>
<td class="label">From</td>
<td>digitaltube/r_cnt_21_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>digitaltube/r_digitalTubeOnes_6_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>i_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>i_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>i_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>i_clk_ibuf/I</td>
</tr>
<tr>
<td>0.683</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>204</td>
<td>IOB12[A]</td>
<td>i_clk_ibuf/O</td>
</tr>
<tr>
<td>1.583</td>
<td>0.901</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C34[3][A]</td>
<td>digitaltube/r_cnt_21_s0/CLK</td>
</tr>
<tr>
<td>1.966</td>
<td>0.382</td>
<td>tC2Q</td>
<td>RR</td>
<td>3</td>
<td>R21C34[3][A]</td>
<td style=" font-weight:bold;">digitaltube/r_cnt_21_s0/Q</td>
</tr>
<tr>
<td>2.379</td>
<td>0.414</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C34[2][A]</td>
<td>digitaltube/n29_s6/I1</td>
</tr>
<tr>
<td>2.841</td>
<td>0.461</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R20C34[2][A]</td>
<td style=" background: #97FFFF;">digitaltube/n29_s6/F</td>
</tr>
<tr>
<td>2.998</td>
<td>0.157</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C33[1][B]</td>
<td>digitaltube/n29_s2/I2</td>
</tr>
<tr>
<td>3.514</td>
<td>0.516</td>
<td>tINS</td>
<td>RR</td>
<td>5</td>
<td>R20C33[1][B]</td>
<td style=" background: #97FFFF;">digitaltube/n29_s2/F</td>
</tr>
<tr>
<td>3.677</td>
<td>0.162</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C32[2][A]</td>
<td>digitaltube/r_cntOnes_4_s3/I1</td>
</tr>
<tr>
<td>4.138</td>
<td>0.461</td>
<td>tINS</td>
<td>RR</td>
<td>25</td>
<td>R20C32[2][A]</td>
<td style=" background: #97FFFF;">digitaltube/r_cntOnes_4_s3/F</td>
</tr>
<tr>
<td>5.074</td>
<td>0.936</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C33[3][A]</td>
<td>digitaltube/r_digitalTubeOnes_6_s2/I3</td>
</tr>
<tr>
<td>5.339</td>
<td>0.265</td>
<td>tINS</td>
<td>RR</td>
<td>7</td>
<td>R18C33[3][A]</td>
<td style=" background: #97FFFF;">digitaltube/r_digitalTubeOnes_6_s2/F</td>
</tr>
<tr>
<td>6.153</td>
<td>0.814</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C33[1][A]</td>
<td style=" font-weight:bold;">digitaltube/r_digitalTubeOnes_6_s0/CE</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>i_clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>i_clk_ibuf/I</td>
</tr>
<tr>
<td>10.682</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>204</td>
<td>IOB12[A]</td>
<td>i_clk_ibuf/O</td>
</tr>
<tr>
<td>11.561</td>
<td>0.878</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C33[1][A]</td>
<td>digitaltube/r_digitalTubeOnes_6_s0/CLK</td>
</tr>
<tr>
<td>11.249</td>
<td>-0.311</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R18C33[1][A]</td>
<td>digitaltube/r_digitalTubeOnes_6_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.022</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>5</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.683, 43.111%; route: 0.901, 56.889%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 1.704, 37.281%; route: 2.484, 54.349%; tC2Q: 0.382, 8.370%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.683, 43.732%; route: 0.878, 56.268%</td>
</tr>
</table>
<h3>Path11</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>5.198</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>6.031</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>11.229</td>
</tr>
<tr>
<td class="label">From</td>
<td>digitaltube/r_cnt_21_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>digitaltube/r_digitalTubeTens_5_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>i_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>i_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>i_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>i_clk_ibuf/I</td>
</tr>
<tr>
<td>0.683</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>204</td>
<td>IOB12[A]</td>
<td>i_clk_ibuf/O</td>
</tr>
<tr>
<td>1.583</td>
<td>0.901</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C34[3][A]</td>
<td>digitaltube/r_cnt_21_s0/CLK</td>
</tr>
<tr>
<td>1.966</td>
<td>0.382</td>
<td>tC2Q</td>
<td>RR</td>
<td>3</td>
<td>R21C34[3][A]</td>
<td style=" font-weight:bold;">digitaltube/r_cnt_21_s0/Q</td>
</tr>
<tr>
<td>2.379</td>
<td>0.414</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C34[2][A]</td>
<td>digitaltube/n29_s6/I1</td>
</tr>
<tr>
<td>2.841</td>
<td>0.461</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R20C34[2][A]</td>
<td style=" background: #97FFFF;">digitaltube/n29_s6/F</td>
</tr>
<tr>
<td>2.998</td>
<td>0.157</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C33[1][B]</td>
<td>digitaltube/n29_s2/I2</td>
</tr>
<tr>
<td>3.514</td>
<td>0.516</td>
<td>tINS</td>
<td>RR</td>
<td>5</td>
<td>R20C33[1][B]</td>
<td style=" background: #97FFFF;">digitaltube/n29_s2/F</td>
</tr>
<tr>
<td>3.677</td>
<td>0.162</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C32[2][A]</td>
<td>digitaltube/r_cntOnes_4_s3/I1</td>
</tr>
<tr>
<td>4.138</td>
<td>0.461</td>
<td>tINS</td>
<td>RR</td>
<td>25</td>
<td>R20C32[2][A]</td>
<td style=" background: #97FFFF;">digitaltube/r_cntOnes_4_s3/F</td>
</tr>
<tr>
<td>5.077</td>
<td>0.939</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C35[1][B]</td>
<td>digitaltube/r_digitalTubeTens_6_s2/I3</td>
</tr>
<tr>
<td>5.538</td>
<td>0.461</td>
<td>tINS</td>
<td>RR</td>
<td>7</td>
<td>R18C35[1][B]</td>
<td style=" background: #97FFFF;">digitaltube/r_digitalTubeTens_6_s2/F</td>
</tr>
<tr>
<td>6.031</td>
<td>0.492</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C35[0][A]</td>
<td style=" font-weight:bold;">digitaltube/r_digitalTubeTens_5_s0/CE</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>i_clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>i_clk_ibuf/I</td>
</tr>
<tr>
<td>10.682</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>204</td>
<td>IOB12[A]</td>
<td>i_clk_ibuf/O</td>
</tr>
<tr>
<td>11.540</td>
<td>0.857</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C35[0][A]</td>
<td>digitaltube/r_digitalTubeTens_5_s0/CLK</td>
</tr>
<tr>
<td>11.229</td>
<td>-0.311</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R17C35[0][A]</td>
<td>digitaltube/r_digitalTubeTens_5_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.043</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>5</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.683, 43.111%; route: 0.901, 56.889%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 1.900, 42.721%; route: 2.165, 48.679%; tC2Q: 0.382, 8.600%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.683, 44.318%; route: 0.857, 55.682%</td>
</tr>
</table>
<h3>Path12</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>5.208</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>6.031</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>11.238</td>
</tr>
<tr>
<td class="label">From</td>
<td>digitaltube/r_cnt_21_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>digitaltube/r_digitalTubeTens_6_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>i_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>i_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>i_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>i_clk_ibuf/I</td>
</tr>
<tr>
<td>0.683</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>204</td>
<td>IOB12[A]</td>
<td>i_clk_ibuf/O</td>
</tr>
<tr>
<td>1.583</td>
<td>0.901</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C34[3][A]</td>
<td>digitaltube/r_cnt_21_s0/CLK</td>
</tr>
<tr>
<td>1.966</td>
<td>0.382</td>
<td>tC2Q</td>
<td>RR</td>
<td>3</td>
<td>R21C34[3][A]</td>
<td style=" font-weight:bold;">digitaltube/r_cnt_21_s0/Q</td>
</tr>
<tr>
<td>2.379</td>
<td>0.414</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C34[2][A]</td>
<td>digitaltube/n29_s6/I1</td>
</tr>
<tr>
<td>2.841</td>
<td>0.461</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R20C34[2][A]</td>
<td style=" background: #97FFFF;">digitaltube/n29_s6/F</td>
</tr>
<tr>
<td>2.998</td>
<td>0.157</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C33[1][B]</td>
<td>digitaltube/n29_s2/I2</td>
</tr>
<tr>
<td>3.514</td>
<td>0.516</td>
<td>tINS</td>
<td>RR</td>
<td>5</td>
<td>R20C33[1][B]</td>
<td style=" background: #97FFFF;">digitaltube/n29_s2/F</td>
</tr>
<tr>
<td>3.677</td>
<td>0.162</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C32[2][A]</td>
<td>digitaltube/r_cntOnes_4_s3/I1</td>
</tr>
<tr>
<td>4.138</td>
<td>0.461</td>
<td>tINS</td>
<td>RR</td>
<td>25</td>
<td>R20C32[2][A]</td>
<td style=" background: #97FFFF;">digitaltube/r_cntOnes_4_s3/F</td>
</tr>
<tr>
<td>5.077</td>
<td>0.939</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C35[1][B]</td>
<td>digitaltube/r_digitalTubeTens_6_s2/I3</td>
</tr>
<tr>
<td>5.538</td>
<td>0.461</td>
<td>tINS</td>
<td>RR</td>
<td>7</td>
<td>R18C35[1][B]</td>
<td style=" background: #97FFFF;">digitaltube/r_digitalTubeTens_6_s2/F</td>
</tr>
<tr>
<td>6.031</td>
<td>0.492</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C34[2][B]</td>
<td style=" font-weight:bold;">digitaltube/r_digitalTubeTens_6_s0/CE</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>i_clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>i_clk_ibuf/I</td>
</tr>
<tr>
<td>10.682</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>204</td>
<td>IOB12[A]</td>
<td>i_clk_ibuf/O</td>
</tr>
<tr>
<td>11.549</td>
<td>0.867</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C34[2][B]</td>
<td>digitaltube/r_digitalTubeTens_6_s0/CLK</td>
</tr>
<tr>
<td>11.238</td>
<td>-0.311</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R17C34[2][B]</td>
<td>digitaltube/r_digitalTubeTens_6_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.034</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>5</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.683, 43.111%; route: 0.901, 56.889%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 1.900, 42.721%; route: 2.165, 48.679%; tC2Q: 0.382, 8.600%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.683, 44.050%; route: 0.867, 55.950%</td>
</tr>
</table>
<h3>Path13</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>5.217</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>6.031</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>11.248</td>
</tr>
<tr>
<td class="label">From</td>
<td>digitaltube/r_cnt_21_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>digitaltube/r_digitalTubeTens_4_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>i_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>i_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>i_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>i_clk_ibuf/I</td>
</tr>
<tr>
<td>0.683</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>204</td>
<td>IOB12[A]</td>
<td>i_clk_ibuf/O</td>
</tr>
<tr>
<td>1.583</td>
<td>0.901</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C34[3][A]</td>
<td>digitaltube/r_cnt_21_s0/CLK</td>
</tr>
<tr>
<td>1.966</td>
<td>0.382</td>
<td>tC2Q</td>
<td>RR</td>
<td>3</td>
<td>R21C34[3][A]</td>
<td style=" font-weight:bold;">digitaltube/r_cnt_21_s0/Q</td>
</tr>
<tr>
<td>2.379</td>
<td>0.414</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C34[2][A]</td>
<td>digitaltube/n29_s6/I1</td>
</tr>
<tr>
<td>2.841</td>
<td>0.461</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R20C34[2][A]</td>
<td style=" background: #97FFFF;">digitaltube/n29_s6/F</td>
</tr>
<tr>
<td>2.998</td>
<td>0.157</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C33[1][B]</td>
<td>digitaltube/n29_s2/I2</td>
</tr>
<tr>
<td>3.514</td>
<td>0.516</td>
<td>tINS</td>
<td>RR</td>
<td>5</td>
<td>R20C33[1][B]</td>
<td style=" background: #97FFFF;">digitaltube/n29_s2/F</td>
</tr>
<tr>
<td>3.677</td>
<td>0.162</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C32[2][A]</td>
<td>digitaltube/r_cntOnes_4_s3/I1</td>
</tr>
<tr>
<td>4.138</td>
<td>0.461</td>
<td>tINS</td>
<td>RR</td>
<td>25</td>
<td>R20C32[2][A]</td>
<td style=" background: #97FFFF;">digitaltube/r_cntOnes_4_s3/F</td>
</tr>
<tr>
<td>5.077</td>
<td>0.939</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C35[1][B]</td>
<td>digitaltube/r_digitalTubeTens_6_s2/I3</td>
</tr>
<tr>
<td>5.538</td>
<td>0.461</td>
<td>tINS</td>
<td>RR</td>
<td>7</td>
<td>R18C35[1][B]</td>
<td style=" background: #97FFFF;">digitaltube/r_digitalTubeTens_6_s2/F</td>
</tr>
<tr>
<td>6.031</td>
<td>0.492</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C33[1][A]</td>
<td style=" font-weight:bold;">digitaltube/r_digitalTubeTens_4_s0/CE</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>i_clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>i_clk_ibuf/I</td>
</tr>
<tr>
<td>10.682</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>204</td>
<td>IOB12[A]</td>
<td>i_clk_ibuf/O</td>
</tr>
<tr>
<td>11.559</td>
<td>0.876</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C33[1][A]</td>
<td>digitaltube/r_digitalTubeTens_4_s0/CLK</td>
</tr>
<tr>
<td>11.248</td>
<td>-0.311</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R17C33[1][A]</td>
<td>digitaltube/r_digitalTubeTens_4_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.024</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>5</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.683, 43.111%; route: 0.901, 56.889%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 1.900, 42.721%; route: 2.165, 48.679%; tC2Q: 0.382, 8.600%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.683, 43.785%; route: 0.876, 56.215%</td>
</tr>
</table>
<h3>Path14</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>5.265</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>6.257</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>11.522</td>
</tr>
<tr>
<td class="label">From</td>
<td>digitaltube/r_cnt_21_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>digitaltube/r_addBuffer_0_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>i_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>i_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>i_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>i_clk_ibuf/I</td>
</tr>
<tr>
<td>0.683</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>204</td>
<td>IOB12[A]</td>
<td>i_clk_ibuf/O</td>
</tr>
<tr>
<td>1.583</td>
<td>0.901</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C34[3][A]</td>
<td>digitaltube/r_cnt_21_s0/CLK</td>
</tr>
<tr>
<td>1.966</td>
<td>0.382</td>
<td>tC2Q</td>
<td>RR</td>
<td>3</td>
<td>R21C34[3][A]</td>
<td style=" font-weight:bold;">digitaltube/r_cnt_21_s0/Q</td>
</tr>
<tr>
<td>2.379</td>
<td>0.414</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C34[2][A]</td>
<td>digitaltube/n29_s6/I1</td>
</tr>
<tr>
<td>2.841</td>
<td>0.461</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R20C34[2][A]</td>
<td style=" background: #97FFFF;">digitaltube/n29_s6/F</td>
</tr>
<tr>
<td>2.998</td>
<td>0.157</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C33[1][B]</td>
<td>digitaltube/n29_s2/I2</td>
</tr>
<tr>
<td>3.514</td>
<td>0.516</td>
<td>tINS</td>
<td>RR</td>
<td>5</td>
<td>R20C33[1][B]</td>
<td style=" background: #97FFFF;">digitaltube/n29_s2/F</td>
</tr>
<tr>
<td>4.448</td>
<td>0.934</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C32[1][B]</td>
<td>digitaltube/n136_s6/I1</td>
</tr>
<tr>
<td>4.964</td>
<td>0.516</td>
<td>tINS</td>
<td>RR</td>
<td>4</td>
<td>R17C32[1][B]</td>
<td style=" background: #97FFFF;">digitaltube/n136_s6/F</td>
</tr>
<tr>
<td>6.257</td>
<td>1.293</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C32[1][A]</td>
<td style=" font-weight:bold;">digitaltube/r_addBuffer_0_s1/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>i_clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>i_clk_ibuf/I</td>
</tr>
<tr>
<td>10.682</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>204</td>
<td>IOB12[A]</td>
<td>i_clk_ibuf/O</td>
</tr>
<tr>
<td>11.586</td>
<td>0.903</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C32[1][A]</td>
<td>digitaltube/r_addBuffer_0_s1/CLK</td>
</tr>
<tr>
<td>11.522</td>
<td>-0.064</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R20C32[1][A]</td>
<td>digitaltube/r_addBuffer_0_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.002</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>4</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.683, 43.111%; route: 0.901, 56.889%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 1.494, 31.960%; route: 2.797, 59.856%; tC2Q: 0.382, 8.184%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.683, 43.043%; route: 0.903, 56.957%</td>
</tr>
</table>
<h3>Path15</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>5.296</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>5.934</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>11.231</td>
</tr>
<tr>
<td class="label">From</td>
<td>digitaltube/r_addBuffer_1_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>digitaltube/r_cntTens_2_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>i_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>i_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>i_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>i_clk_ibuf/I</td>
</tr>
<tr>
<td>0.683</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>204</td>
<td>IOB12[A]</td>
<td>i_clk_ibuf/O</td>
</tr>
<tr>
<td>1.586</td>
<td>0.903</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C32[3][A]</td>
<td>digitaltube/r_addBuffer_1_s1/CLK</td>
</tr>
<tr>
<td>1.968</td>
<td>0.382</td>
<td>tC2Q</td>
<td>RR</td>
<td>1</td>
<td>R20C32[3][A]</td>
<td style=" font-weight:bold;">digitaltube/r_addBuffer_1_s1/Q</td>
</tr>
<tr>
<td>3.163</td>
<td>1.195</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>R18C32[0][B]</td>
<td>digitaltube/n192_s/I1</td>
</tr>
<tr>
<td>3.656</td>
<td>0.493</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R18C32[0][B]</td>
<td style=" background: #97FFFF;">digitaltube/n192_s/COUT</td>
</tr>
<tr>
<td>3.656</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>R18C32[1][A]</td>
<td>digitaltube/n191_s/CIN</td>
</tr>
<tr>
<td>3.706</td>
<td>0.050</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R18C32[1][A]</td>
<td style=" background: #97FFFF;">digitaltube/n191_s/COUT</td>
</tr>
<tr>
<td>3.706</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>R18C32[1][B]</td>
<td>digitaltube/n190_s/CIN</td>
</tr>
<tr>
<td>4.002</td>
<td>0.296</td>
<td>tINS</td>
<td>RR</td>
<td>3</td>
<td>R18C32[1][B]</td>
<td style=" background: #97FFFF;">digitaltube/n190_s/SUM</td>
</tr>
<tr>
<td>4.142</td>
<td>0.140</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C32[2][B]</td>
<td>digitaltube/n224_s2/I2</td>
</tr>
<tr>
<td>4.668</td>
<td>0.526</td>
<td>tINS</td>
<td>RR</td>
<td>4</td>
<td>R18C32[2][B]</td>
<td style=" background: #97FFFF;">digitaltube/n224_s2/F</td>
</tr>
<tr>
<td>5.021</td>
<td>0.352</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C33[0][B]</td>
<td>digitaltube/r_cntTens_4_s4/I0</td>
</tr>
<tr>
<td>5.547</td>
<td>0.526</td>
<td>tINS</td>
<td>RR</td>
<td>5</td>
<td>R17C33[0][B]</td>
<td style=" background: #97FFFF;">digitaltube/r_cntTens_4_s4/F</td>
</tr>
<tr>
<td>5.934</td>
<td>0.387</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C35[1][A]</td>
<td style=" font-weight:bold;">digitaltube/r_cntTens_2_s1/CE</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>i_clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>i_clk_ibuf/I</td>
</tr>
<tr>
<td>10.682</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>204</td>
<td>IOB12[A]</td>
<td>i_clk_ibuf/O</td>
</tr>
<tr>
<td>11.542</td>
<td>0.859</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C35[1][A]</td>
<td>digitaltube/r_cntTens_2_s1/CLK</td>
</tr>
<tr>
<td>11.231</td>
<td>-0.311</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R18C35[1][A]</td>
<td>digitaltube/r_cntTens_2_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.044</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>5</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.683, 43.043%; route: 0.903, 56.957%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 1.891, 43.490%; route: 2.075, 47.715%; tC2Q: 0.382, 8.796%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.683, 44.264%; route: 0.859, 55.736%</td>
</tr>
</table>
<h3>Path16</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>5.376</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>5.873</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>11.249</td>
</tr>
<tr>
<td class="label">From</td>
<td>digitaltube/r_cnt_21_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>digitaltube/r_digitalTubeTens_3_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>i_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>i_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>i_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>i_clk_ibuf/I</td>
</tr>
<tr>
<td>0.683</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>204</td>
<td>IOB12[A]</td>
<td>i_clk_ibuf/O</td>
</tr>
<tr>
<td>1.583</td>
<td>0.901</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C34[3][A]</td>
<td>digitaltube/r_cnt_21_s0/CLK</td>
</tr>
<tr>
<td>1.966</td>
<td>0.382</td>
<td>tC2Q</td>
<td>RR</td>
<td>3</td>
<td>R21C34[3][A]</td>
<td style=" font-weight:bold;">digitaltube/r_cnt_21_s0/Q</td>
</tr>
<tr>
<td>2.379</td>
<td>0.414</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C34[2][A]</td>
<td>digitaltube/n29_s6/I1</td>
</tr>
<tr>
<td>2.841</td>
<td>0.461</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R20C34[2][A]</td>
<td style=" background: #97FFFF;">digitaltube/n29_s6/F</td>
</tr>
<tr>
<td>2.998</td>
<td>0.157</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C33[1][B]</td>
<td>digitaltube/n29_s2/I2</td>
</tr>
<tr>
<td>3.514</td>
<td>0.516</td>
<td>tINS</td>
<td>RR</td>
<td>5</td>
<td>R20C33[1][B]</td>
<td style=" background: #97FFFF;">digitaltube/n29_s2/F</td>
</tr>
<tr>
<td>3.677</td>
<td>0.162</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C32[2][A]</td>
<td>digitaltube/r_cntOnes_4_s3/I1</td>
</tr>
<tr>
<td>4.138</td>
<td>0.461</td>
<td>tINS</td>
<td>RR</td>
<td>25</td>
<td>R20C32[2][A]</td>
<td style=" background: #97FFFF;">digitaltube/r_cntOnes_4_s3/F</td>
</tr>
<tr>
<td>5.077</td>
<td>0.939</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C35[1][B]</td>
<td>digitaltube/r_digitalTubeTens_6_s2/I3</td>
</tr>
<tr>
<td>5.538</td>
<td>0.461</td>
<td>tINS</td>
<td>RR</td>
<td>7</td>
<td>R18C35[1][B]</td>
<td style=" background: #97FFFF;">digitaltube/r_digitalTubeTens_6_s2/F</td>
</tr>
<tr>
<td>5.873</td>
<td>0.335</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C33[0][A]</td>
<td style=" font-weight:bold;">digitaltube/r_digitalTubeTens_3_s0/CE</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>i_clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>i_clk_ibuf/I</td>
</tr>
<tr>
<td>10.682</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>204</td>
<td>IOB12[A]</td>
<td>i_clk_ibuf/O</td>
</tr>
<tr>
<td>11.561</td>
<td>0.878</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C33[0][A]</td>
<td>digitaltube/r_digitalTubeTens_3_s0/CLK</td>
</tr>
<tr>
<td>11.249</td>
<td>-0.311</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R18C33[0][A]</td>
<td>digitaltube/r_digitalTubeTens_3_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.022</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>5</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.683, 43.111%; route: 0.901, 56.889%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 1.900, 44.289%; route: 2.007, 46.795%; tC2Q: 0.382, 8.916%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.683, 43.732%; route: 0.878, 56.268%</td>
</tr>
</table>
<h3>Path17</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>5.397</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>6.124</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>11.522</td>
</tr>
<tr>
<td class="label">From</td>
<td>digitaltube/r_cnt_21_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>digitaltube/r_addBuffer_1_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>i_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>i_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>i_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>i_clk_ibuf/I</td>
</tr>
<tr>
<td>0.683</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>204</td>
<td>IOB12[A]</td>
<td>i_clk_ibuf/O</td>
</tr>
<tr>
<td>1.583</td>
<td>0.901</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C34[3][A]</td>
<td>digitaltube/r_cnt_21_s0/CLK</td>
</tr>
<tr>
<td>1.966</td>
<td>0.382</td>
<td>tC2Q</td>
<td>RR</td>
<td>3</td>
<td>R21C34[3][A]</td>
<td style=" font-weight:bold;">digitaltube/r_cnt_21_s0/Q</td>
</tr>
<tr>
<td>2.379</td>
<td>0.414</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C34[2][A]</td>
<td>digitaltube/n29_s6/I1</td>
</tr>
<tr>
<td>2.841</td>
<td>0.461</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R20C34[2][A]</td>
<td style=" background: #97FFFF;">digitaltube/n29_s6/F</td>
</tr>
<tr>
<td>2.998</td>
<td>0.157</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C33[1][B]</td>
<td>digitaltube/n29_s2/I2</td>
</tr>
<tr>
<td>3.514</td>
<td>0.516</td>
<td>tINS</td>
<td>RR</td>
<td>5</td>
<td>R20C33[1][B]</td>
<td style=" background: #97FFFF;">digitaltube/n29_s2/F</td>
</tr>
<tr>
<td>4.448</td>
<td>0.934</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C32[1][B]</td>
<td>digitaltube/n136_s6/I1</td>
</tr>
<tr>
<td>4.964</td>
<td>0.516</td>
<td>tINS</td>
<td>RR</td>
<td>4</td>
<td>R17C32[1][B]</td>
<td style=" background: #97FFFF;">digitaltube/n136_s6/F</td>
</tr>
<tr>
<td>6.124</td>
<td>1.160</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C32[3][A]</td>
<td style=" font-weight:bold;">digitaltube/r_addBuffer_1_s1/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>i_clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>i_clk_ibuf/I</td>
</tr>
<tr>
<td>10.682</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>204</td>
<td>IOB12[A]</td>
<td>i_clk_ibuf/O</td>
</tr>
<tr>
<td>11.586</td>
<td>0.903</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C32[3][A]</td>
<td>digitaltube/r_addBuffer_1_s1/CLK</td>
</tr>
<tr>
<td>11.522</td>
<td>-0.064</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R20C32[3][A]</td>
<td>digitaltube/r_addBuffer_1_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.002</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>4</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.683, 43.111%; route: 0.901, 56.889%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 1.494, 32.893%; route: 2.665, 58.684%; tC2Q: 0.382, 8.423%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.683, 43.043%; route: 0.903, 56.957%</td>
</tr>
</table>
<h3>Path18</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>5.415</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>6.072</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>11.488</td>
</tr>
<tr>
<td class="label">From</td>
<td>led/r_cnt_11_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>led/r_cnt_0_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>i_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>i_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>i_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>i_clk_ibuf/I</td>
</tr>
<tr>
<td>0.683</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>204</td>
<td>IOB12[A]</td>
<td>i_clk_ibuf/O</td>
</tr>
<tr>
<td>1.551</td>
<td>0.869</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C38[1][A]</td>
<td>led/r_cnt_11_s0/CLK</td>
</tr>
<tr>
<td>1.934</td>
<td>0.382</td>
<td>tC2Q</td>
<td>RR</td>
<td>3</td>
<td>R18C38[1][A]</td>
<td style=" font-weight:bold;">led/r_cnt_11_s0/Q</td>
</tr>
<tr>
<td>2.852</td>
<td>0.919</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C37[1][A]</td>
<td>led/n41_s9/I1</td>
</tr>
<tr>
<td>3.379</td>
<td>0.526</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R20C37[1][A]</td>
<td style=" background: #97FFFF;">led/n41_s9/F</td>
</tr>
<tr>
<td>3.536</td>
<td>0.157</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C37[3][A]</td>
<td>led/n41_s4/I2</td>
</tr>
<tr>
<td>4.034</td>
<td>0.498</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R21C37[3][A]</td>
<td style=" background: #97FFFF;">led/n41_s4/F</td>
</tr>
<tr>
<td>4.191</td>
<td>0.157</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C37[0][A]</td>
<td>led/n41_s0/I3</td>
</tr>
<tr>
<td>4.652</td>
<td>0.461</td>
<td>tINS</td>
<td>RR</td>
<td>21</td>
<td>R20C37[0][A]</td>
<td style=" background: #97FFFF;">led/n41_s0/F</td>
</tr>
<tr>
<td>5.611</td>
<td>0.959</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C38[1][B]</td>
<td>led/n98_s2/I1</td>
</tr>
<tr>
<td>6.072</td>
<td>0.461</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R18C38[1][B]</td>
<td style=" background: #97FFFF;">led/n98_s2/F</td>
</tr>
<tr>
<td>6.072</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C38[1][B]</td>
<td style=" font-weight:bold;">led/r_cnt_0_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>i_clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>i_clk_ibuf/I</td>
</tr>
<tr>
<td>10.682</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>204</td>
<td>IOB12[A]</td>
<td>i_clk_ibuf/O</td>
</tr>
<tr>
<td>11.551</td>
<td>0.869</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C38[1][B]</td>
<td>led/r_cnt_0_s0/CLK</td>
</tr>
<tr>
<td>11.488</td>
<td>-0.064</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R18C38[1][B]</td>
<td>led/r_cnt_0_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>5</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.683, 43.997%; route: 0.869, 56.003%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 1.946, 43.047%; route: 2.193, 48.493%; tC2Q: 0.382, 8.460%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.683, 43.997%; route: 0.869, 56.003%</td>
</tr>
</table>
<h3>Path19</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>5.437</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>6.060</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>11.497</td>
</tr>
<tr>
<td class="label">From</td>
<td>led/r_cnt_11_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>led/r_cnt_12_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>i_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>i_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>i_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>i_clk_ibuf/I</td>
</tr>
<tr>
<td>0.683</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>204</td>
<td>IOB12[A]</td>
<td>i_clk_ibuf/O</td>
</tr>
<tr>
<td>1.551</td>
<td>0.869</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C38[1][A]</td>
<td>led/r_cnt_11_s0/CLK</td>
</tr>
<tr>
<td>1.934</td>
<td>0.382</td>
<td>tC2Q</td>
<td>RR</td>
<td>3</td>
<td>R18C38[1][A]</td>
<td style=" font-weight:bold;">led/r_cnt_11_s0/Q</td>
</tr>
<tr>
<td>2.852</td>
<td>0.919</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C37[1][A]</td>
<td>led/n41_s9/I1</td>
</tr>
<tr>
<td>3.379</td>
<td>0.526</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R20C37[1][A]</td>
<td style=" background: #97FFFF;">led/n41_s9/F</td>
</tr>
<tr>
<td>3.536</td>
<td>0.157</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C37[3][A]</td>
<td>led/n41_s4/I2</td>
</tr>
<tr>
<td>4.034</td>
<td>0.498</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R21C37[3][A]</td>
<td style=" background: #97FFFF;">led/n41_s4/F</td>
</tr>
<tr>
<td>4.191</td>
<td>0.157</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C37[0][A]</td>
<td>led/n41_s0/I3</td>
</tr>
<tr>
<td>4.652</td>
<td>0.461</td>
<td>tINS</td>
<td>RR</td>
<td>21</td>
<td>R20C37[0][A]</td>
<td style=" background: #97FFFF;">led/n41_s0/F</td>
</tr>
<tr>
<td>5.534</td>
<td>0.881</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C37[0][B]</td>
<td>led/n86_s2/I2</td>
</tr>
<tr>
<td>6.060</td>
<td>0.526</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R18C37[0][B]</td>
<td style=" background: #97FFFF;">led/n86_s2/F</td>
</tr>
<tr>
<td>6.060</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C37[0][B]</td>
<td style=" font-weight:bold;">led/r_cnt_12_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>i_clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>i_clk_ibuf/I</td>
</tr>
<tr>
<td>10.682</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>204</td>
<td>IOB12[A]</td>
<td>i_clk_ibuf/O</td>
</tr>
<tr>
<td>11.561</td>
<td>0.878</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C37[0][B]</td>
<td>led/r_cnt_12_s0/CLK</td>
</tr>
<tr>
<td>11.497</td>
<td>-0.064</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R18C37[0][B]</td>
<td>led/r_cnt_12_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.009</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>5</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.683, 43.997%; route: 0.869, 56.003%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 2.011, 44.608%; route: 2.115, 46.909%; tC2Q: 0.382, 8.484%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.683, 43.732%; route: 0.878, 56.268%</td>
</tr>
</table>
<h3>Path20</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>5.445</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>6.077</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>11.522</td>
</tr>
<tr>
<td class="label">From</td>
<td>digitaltube/r_cnt_21_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>digitaltube/r_cnt_8_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>i_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>i_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>i_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>i_clk_ibuf/I</td>
</tr>
<tr>
<td>0.683</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>204</td>
<td>IOB12[A]</td>
<td>i_clk_ibuf/O</td>
</tr>
<tr>
<td>1.583</td>
<td>0.901</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C34[3][A]</td>
<td>digitaltube/r_cnt_21_s0/CLK</td>
</tr>
<tr>
<td>1.966</td>
<td>0.382</td>
<td>tC2Q</td>
<td>RR</td>
<td>3</td>
<td>R21C34[3][A]</td>
<td style=" font-weight:bold;">digitaltube/r_cnt_21_s0/Q</td>
</tr>
<tr>
<td>2.379</td>
<td>0.414</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C34[2][A]</td>
<td>digitaltube/n29_s6/I1</td>
</tr>
<tr>
<td>2.841</td>
<td>0.461</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R20C34[2][A]</td>
<td style=" background: #97FFFF;">digitaltube/n29_s6/F</td>
</tr>
<tr>
<td>2.998</td>
<td>0.157</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C33[1][B]</td>
<td>digitaltube/n29_s2/I2</td>
</tr>
<tr>
<td>3.514</td>
<td>0.516</td>
<td>tINS</td>
<td>RR</td>
<td>5</td>
<td>R20C33[1][B]</td>
<td style=" background: #97FFFF;">digitaltube/n29_s2/F</td>
</tr>
<tr>
<td>3.677</td>
<td>0.162</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C32[2][A]</td>
<td>digitaltube/r_cntOnes_4_s3/I1</td>
</tr>
<tr>
<td>4.138</td>
<td>0.461</td>
<td>tINS</td>
<td>RR</td>
<td>25</td>
<td>R20C32[2][A]</td>
<td style=" background: #97FFFF;">digitaltube/r_cntOnes_4_s3/F</td>
</tr>
<tr>
<td>5.616</td>
<td>1.477</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C34[0][B]</td>
<td>digitaltube/n70_s5/I0</td>
</tr>
<tr>
<td>6.077</td>
<td>0.461</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R20C34[0][B]</td>
<td style=" background: #97FFFF;">digitaltube/n70_s5/F</td>
</tr>
<tr>
<td>6.077</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C34[0][B]</td>
<td style=" font-weight:bold;">digitaltube/r_cnt_8_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>i_clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>i_clk_ibuf/I</td>
</tr>
<tr>
<td>10.682</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>204</td>
<td>IOB12[A]</td>
<td>i_clk_ibuf/O</td>
</tr>
<tr>
<td>11.586</td>
<td>0.903</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C34[0][B]</td>
<td>digitaltube/r_cnt_8_s0/CLK</td>
</tr>
<tr>
<td>11.522</td>
<td>-0.064</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R20C34[0][B]</td>
<td>digitaltube/r_cnt_8_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.002</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>5</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.683, 43.111%; route: 0.901, 56.889%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 1.900, 42.281%; route: 2.211, 49.207%; tC2Q: 0.382, 8.512%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.683, 43.043%; route: 0.903, 56.957%</td>
</tr>
</table>
<h3>Path21</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>5.449</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>6.077</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>11.526</td>
</tr>
<tr>
<td class="label">From</td>
<td>digitaltube/r_cnt_21_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>digitaltube/r_cnt_9_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>i_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>i_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>i_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>i_clk_ibuf/I</td>
</tr>
<tr>
<td>0.683</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>204</td>
<td>IOB12[A]</td>
<td>i_clk_ibuf/O</td>
</tr>
<tr>
<td>1.583</td>
<td>0.901</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C34[3][A]</td>
<td>digitaltube/r_cnt_21_s0/CLK</td>
</tr>
<tr>
<td>1.966</td>
<td>0.382</td>
<td>tC2Q</td>
<td>RR</td>
<td>3</td>
<td>R21C34[3][A]</td>
<td style=" font-weight:bold;">digitaltube/r_cnt_21_s0/Q</td>
</tr>
<tr>
<td>2.379</td>
<td>0.414</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C34[2][A]</td>
<td>digitaltube/n29_s6/I1</td>
</tr>
<tr>
<td>2.841</td>
<td>0.461</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R20C34[2][A]</td>
<td style=" background: #97FFFF;">digitaltube/n29_s6/F</td>
</tr>
<tr>
<td>2.998</td>
<td>0.157</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C33[1][B]</td>
<td>digitaltube/n29_s2/I2</td>
</tr>
<tr>
<td>3.514</td>
<td>0.516</td>
<td>tINS</td>
<td>RR</td>
<td>5</td>
<td>R20C33[1][B]</td>
<td style=" background: #97FFFF;">digitaltube/n29_s2/F</td>
</tr>
<tr>
<td>3.677</td>
<td>0.162</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C32[2][A]</td>
<td>digitaltube/r_cntOnes_4_s3/I1</td>
</tr>
<tr>
<td>4.138</td>
<td>0.461</td>
<td>tINS</td>
<td>RR</td>
<td>25</td>
<td>R20C32[2][A]</td>
<td style=" background: #97FFFF;">digitaltube/r_cntOnes_4_s3/F</td>
</tr>
<tr>
<td>5.616</td>
<td>1.477</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R22C33[1][A]</td>
<td>digitaltube/n69_s2/I0</td>
</tr>
<tr>
<td>6.077</td>
<td>0.461</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R22C33[1][A]</td>
<td style=" background: #97FFFF;">digitaltube/n69_s2/F</td>
</tr>
<tr>
<td>6.077</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R22C33[1][A]</td>
<td style=" font-weight:bold;">digitaltube/r_cnt_9_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>i_clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>i_clk_ibuf/I</td>
</tr>
<tr>
<td>10.682</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>204</td>
<td>IOB12[A]</td>
<td>i_clk_ibuf/O</td>
</tr>
<tr>
<td>11.590</td>
<td>0.908</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R22C33[1][A]</td>
<td>digitaltube/r_cnt_9_s0/CLK</td>
</tr>
<tr>
<td>11.526</td>
<td>-0.064</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R22C33[1][A]</td>
<td>digitaltube/r_cnt_9_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.007</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>5</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.683, 43.111%; route: 0.901, 56.889%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 1.900, 42.281%; route: 2.211, 49.207%; tC2Q: 0.382, 8.512%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.683, 42.925%; route: 0.908, 57.075%</td>
</tr>
</table>
<h3>Path22</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>5.466</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>6.031</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>11.497</td>
</tr>
<tr>
<td class="label">From</td>
<td>led/r_cnt_11_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>led/r_cnt_7_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>i_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>i_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>i_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>i_clk_ibuf/I</td>
</tr>
<tr>
<td>0.683</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>204</td>
<td>IOB12[A]</td>
<td>i_clk_ibuf/O</td>
</tr>
<tr>
<td>1.551</td>
<td>0.869</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C38[1][A]</td>
<td>led/r_cnt_11_s0/CLK</td>
</tr>
<tr>
<td>1.934</td>
<td>0.382</td>
<td>tC2Q</td>
<td>RR</td>
<td>3</td>
<td>R18C38[1][A]</td>
<td style=" font-weight:bold;">led/r_cnt_11_s0/Q</td>
</tr>
<tr>
<td>2.852</td>
<td>0.919</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C37[1][A]</td>
<td>led/n41_s9/I1</td>
</tr>
<tr>
<td>3.379</td>
<td>0.526</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R20C37[1][A]</td>
<td style=" background: #97FFFF;">led/n41_s9/F</td>
</tr>
<tr>
<td>3.536</td>
<td>0.157</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C37[3][A]</td>
<td>led/n41_s4/I2</td>
</tr>
<tr>
<td>4.034</td>
<td>0.498</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R21C37[3][A]</td>
<td style=" background: #97FFFF;">led/n41_s4/F</td>
</tr>
<tr>
<td>4.191</td>
<td>0.157</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C37[0][A]</td>
<td>led/n41_s0/I3</td>
</tr>
<tr>
<td>4.652</td>
<td>0.461</td>
<td>tINS</td>
<td>RR</td>
<td>21</td>
<td>R20C37[0][A]</td>
<td style=" background: #97FFFF;">led/n41_s0/F</td>
</tr>
<tr>
<td>5.534</td>
<td>0.881</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C37[3][A]</td>
<td>led/n91_s2/I0</td>
</tr>
<tr>
<td>6.031</td>
<td>0.498</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R18C37[3][A]</td>
<td style=" background: #97FFFF;">led/n91_s2/F</td>
</tr>
<tr>
<td>6.031</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C37[3][A]</td>
<td style=" font-weight:bold;">led/r_cnt_7_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>i_clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>i_clk_ibuf/I</td>
</tr>
<tr>
<td>10.682</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>204</td>
<td>IOB12[A]</td>
<td>i_clk_ibuf/O</td>
</tr>
<tr>
<td>11.561</td>
<td>0.878</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C37[3][A]</td>
<td>led/r_cnt_7_s0/CLK</td>
</tr>
<tr>
<td>11.497</td>
<td>-0.064</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R18C37[3][A]</td>
<td>led/r_cnt_7_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.009</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>5</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.683, 43.997%; route: 0.869, 56.003%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 1.983, 44.252%; route: 2.115, 47.210%; tC2Q: 0.382, 8.538%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.683, 43.732%; route: 0.878, 56.268%</td>
</tr>
</table>
<h3>Path23</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>5.494</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>5.744</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>11.238</td>
</tr>
<tr>
<td class="label">From</td>
<td>digitaltube/r_addBuffer_1_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>digitaltube/r_cntTens_0_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>i_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>i_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>i_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>i_clk_ibuf/I</td>
</tr>
<tr>
<td>0.683</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>204</td>
<td>IOB12[A]</td>
<td>i_clk_ibuf/O</td>
</tr>
<tr>
<td>1.586</td>
<td>0.903</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C32[3][A]</td>
<td>digitaltube/r_addBuffer_1_s1/CLK</td>
</tr>
<tr>
<td>1.968</td>
<td>0.382</td>
<td>tC2Q</td>
<td>RR</td>
<td>1</td>
<td>R20C32[3][A]</td>
<td style=" font-weight:bold;">digitaltube/r_addBuffer_1_s1/Q</td>
</tr>
<tr>
<td>3.163</td>
<td>1.195</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>R18C32[0][B]</td>
<td>digitaltube/n192_s/I1</td>
</tr>
<tr>
<td>3.656</td>
<td>0.493</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R18C32[0][B]</td>
<td style=" background: #97FFFF;">digitaltube/n192_s/COUT</td>
</tr>
<tr>
<td>3.656</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>R18C32[1][A]</td>
<td>digitaltube/n191_s/CIN</td>
</tr>
<tr>
<td>3.706</td>
<td>0.050</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R18C32[1][A]</td>
<td style=" background: #97FFFF;">digitaltube/n191_s/COUT</td>
</tr>
<tr>
<td>3.706</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>R18C32[1][B]</td>
<td>digitaltube/n190_s/CIN</td>
</tr>
<tr>
<td>4.002</td>
<td>0.296</td>
<td>tINS</td>
<td>RR</td>
<td>3</td>
<td>R18C32[1][B]</td>
<td style=" background: #97FFFF;">digitaltube/n190_s/SUM</td>
</tr>
<tr>
<td>4.142</td>
<td>0.140</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C32[2][B]</td>
<td>digitaltube/n224_s2/I2</td>
</tr>
<tr>
<td>4.668</td>
<td>0.526</td>
<td>tINS</td>
<td>RR</td>
<td>4</td>
<td>R18C32[2][B]</td>
<td style=" background: #97FFFF;">digitaltube/n224_s2/F</td>
</tr>
<tr>
<td>5.021</td>
<td>0.352</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C33[0][B]</td>
<td>digitaltube/r_cntTens_4_s4/I0</td>
</tr>
<tr>
<td>5.547</td>
<td>0.526</td>
<td>tINS</td>
<td>RR</td>
<td>5</td>
<td>R17C33[0][B]</td>
<td style=" background: #97FFFF;">digitaltube/r_cntTens_4_s4/F</td>
</tr>
<tr>
<td>5.744</td>
<td>0.197</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C34[0][B]</td>
<td style=" font-weight:bold;">digitaltube/r_cntTens_0_s1/CE</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>i_clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>i_clk_ibuf/I</td>
</tr>
<tr>
<td>10.682</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>204</td>
<td>IOB12[A]</td>
<td>i_clk_ibuf/O</td>
</tr>
<tr>
<td>11.549</td>
<td>0.867</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C34[0][B]</td>
<td>digitaltube/r_cntTens_0_s1/CLK</td>
</tr>
<tr>
<td>11.238</td>
<td>-0.311</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R17C34[0][B]</td>
<td>digitaltube/r_cntTens_0_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.036</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>5</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.683, 43.043%; route: 0.903, 56.957%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 1.891, 45.476%; route: 1.885, 45.326%; tC2Q: 0.382, 9.197%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.683, 44.050%; route: 0.867, 55.950%</td>
</tr>
</table>
<h3>Path24</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>5.494</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>5.744</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>11.238</td>
</tr>
<tr>
<td class="label">From</td>
<td>digitaltube/r_addBuffer_1_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>digitaltube/r_cntTens_4_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>i_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>i_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>i_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>i_clk_ibuf/I</td>
</tr>
<tr>
<td>0.683</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>204</td>
<td>IOB12[A]</td>
<td>i_clk_ibuf/O</td>
</tr>
<tr>
<td>1.586</td>
<td>0.903</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C32[3][A]</td>
<td>digitaltube/r_addBuffer_1_s1/CLK</td>
</tr>
<tr>
<td>1.968</td>
<td>0.382</td>
<td>tC2Q</td>
<td>RR</td>
<td>1</td>
<td>R20C32[3][A]</td>
<td style=" font-weight:bold;">digitaltube/r_addBuffer_1_s1/Q</td>
</tr>
<tr>
<td>3.163</td>
<td>1.195</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>R18C32[0][B]</td>
<td>digitaltube/n192_s/I1</td>
</tr>
<tr>
<td>3.656</td>
<td>0.493</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R18C32[0][B]</td>
<td style=" background: #97FFFF;">digitaltube/n192_s/COUT</td>
</tr>
<tr>
<td>3.656</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>R18C32[1][A]</td>
<td>digitaltube/n191_s/CIN</td>
</tr>
<tr>
<td>3.706</td>
<td>0.050</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R18C32[1][A]</td>
<td style=" background: #97FFFF;">digitaltube/n191_s/COUT</td>
</tr>
<tr>
<td>3.706</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>R18C32[1][B]</td>
<td>digitaltube/n190_s/CIN</td>
</tr>
<tr>
<td>4.002</td>
<td>0.296</td>
<td>tINS</td>
<td>RR</td>
<td>3</td>
<td>R18C32[1][B]</td>
<td style=" background: #97FFFF;">digitaltube/n190_s/SUM</td>
</tr>
<tr>
<td>4.142</td>
<td>0.140</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C32[2][B]</td>
<td>digitaltube/n224_s2/I2</td>
</tr>
<tr>
<td>4.668</td>
<td>0.526</td>
<td>tINS</td>
<td>RR</td>
<td>4</td>
<td>R18C32[2][B]</td>
<td style=" background: #97FFFF;">digitaltube/n224_s2/F</td>
</tr>
<tr>
<td>5.021</td>
<td>0.352</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C33[0][B]</td>
<td>digitaltube/r_cntTens_4_s4/I0</td>
</tr>
<tr>
<td>5.547</td>
<td>0.526</td>
<td>tINS</td>
<td>RR</td>
<td>5</td>
<td>R17C33[0][B]</td>
<td style=" background: #97FFFF;">digitaltube/r_cntTens_4_s4/F</td>
</tr>
<tr>
<td>5.744</td>
<td>0.197</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C34[0][A]</td>
<td style=" font-weight:bold;">digitaltube/r_cntTens_4_s1/CE</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>i_clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>i_clk_ibuf/I</td>
</tr>
<tr>
<td>10.682</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>204</td>
<td>IOB12[A]</td>
<td>i_clk_ibuf/O</td>
</tr>
<tr>
<td>11.549</td>
<td>0.867</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C34[0][A]</td>
<td>digitaltube/r_cntTens_4_s1/CLK</td>
</tr>
<tr>
<td>11.238</td>
<td>-0.311</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R17C34[0][A]</td>
<td>digitaltube/r_cntTens_4_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.036</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>5</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.683, 43.043%; route: 0.903, 56.957%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 1.891, 45.476%; route: 1.885, 45.326%; tC2Q: 0.382, 9.197%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.683, 44.050%; route: 0.867, 55.950%</td>
</tr>
</table>
<h3>Path25</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>5.499</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>5.987</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>11.486</td>
</tr>
<tr>
<td class="label">From</td>
<td>button3/r_cnt_2_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>button3/r_cnt_16_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>i_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>i_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>i_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>i_clk_ibuf/I</td>
</tr>
<tr>
<td>0.683</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>204</td>
<td>IOB12[A]</td>
<td>i_clk_ibuf/O</td>
</tr>
<tr>
<td>1.561</td>
<td>0.878</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C41[1][A]</td>
<td>button3/r_cnt_2_s0/CLK</td>
</tr>
<tr>
<td>1.943</td>
<td>0.382</td>
<td>tC2Q</td>
<td>RR</td>
<td>3</td>
<td>R18C41[1][A]</td>
<td style=" font-weight:bold;">button3/r_cnt_2_s0/Q</td>
</tr>
<tr>
<td>2.836</td>
<td>0.893</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C40[3][A]</td>
<td>button3/n89_s3/I2</td>
</tr>
<tr>
<td>3.251</td>
<td>0.415</td>
<td>tINS</td>
<td>RR</td>
<td>4</td>
<td>R20C40[3][A]</td>
<td style=" background: #97FFFF;">button3/n89_s3/F</td>
</tr>
<tr>
<td>3.411</td>
<td>0.160</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C41[2][A]</td>
<td>button3/n85_s3/I2</td>
</tr>
<tr>
<td>3.927</td>
<td>0.516</td>
<td>tINS</td>
<td>RR</td>
<td>6</td>
<td>R20C41[2][A]</td>
<td style=" background: #97FFFF;">button3/n85_s3/F</td>
</tr>
<tr>
<td>3.934</td>
<td>0.008</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C41[1][B]</td>
<td>button3/n80_s3/I0</td>
</tr>
<tr>
<td>4.396</td>
<td>0.461</td>
<td>tINS</td>
<td>RR</td>
<td>10</td>
<td>R20C41[1][B]</td>
<td style=" background: #97FFFF;">button3/n80_s3/F</td>
</tr>
<tr>
<td>5.526</td>
<td>1.130</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C40[2][A]</td>
<td>button3/n77_s2/I0</td>
</tr>
<tr>
<td>5.987</td>
<td>0.461</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R17C40[2][A]</td>
<td style=" background: #97FFFF;">button3/n77_s2/F</td>
</tr>
<tr>
<td>5.987</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C40[2][A]</td>
<td style=" font-weight:bold;">button3/r_cnt_16_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>i_clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>i_clk_ibuf/I</td>
</tr>
<tr>
<td>10.682</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>204</td>
<td>IOB12[A]</td>
<td>i_clk_ibuf/O</td>
</tr>
<tr>
<td>11.549</td>
<td>0.867</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C40[2][A]</td>
<td>button3/r_cnt_16_s0/CLK</td>
</tr>
<tr>
<td>11.486</td>
<td>-0.064</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R17C40[2][A]</td>
<td>button3/r_cnt_16_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.011</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>5</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.683, 43.732%; route: 0.878, 56.268%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 1.854, 41.881%; route: 2.190, 49.478%; tC2Q: 0.382, 8.642%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.683, 44.050%; route: 0.867, 55.950%</td>
</tr>
</table>
<h3><a name="Hold_Analysis">Hold Analysis Report</a></h3>
<h4>Report Command:report_timing -hold -max_paths 25 -max_common_paths 1</h4>
<h3>Path1</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.374</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.445</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.071</td>
</tr>
<tr>
<td class="label">From</td>
<td>led/r_cnt_13_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>led/r_cnt_13_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>i_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>i_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>i_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>i_clk_ibuf/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>204</td>
<td>IOB12[A]</td>
<td>i_clk_ibuf/O</td>
</tr>
<tr>
<td>1.070</td>
<td>0.394</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R22C38[0][A]</td>
<td>led/r_cnt_13_s0/CLK</td>
</tr>
<tr>
<td>1.246</td>
<td>0.176</td>
<td>tC2Q</td>
<td>RF</td>
<td>3</td>
<td>R22C38[0][A]</td>
<td style=" font-weight:bold;">led/r_cnt_13_s0/Q</td>
</tr>
<tr>
<td>1.253</td>
<td>0.008</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R22C38[0][A]</td>
<td>led/n85_s2/I1</td>
</tr>
<tr>
<td>1.445</td>
<td>0.191</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R22C38[0][A]</td>
<td style=" background: #97FFFF;">led/n85_s2/F</td>
</tr>
<tr>
<td>1.445</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R22C38[0][A]</td>
<td style=" font-weight:bold;">led/r_cnt_13_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>i_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>i_clk_ibuf/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>204</td>
<td>IOB12[A]</td>
<td>i_clk_ibuf/O</td>
</tr>
<tr>
<td>1.070</td>
<td>0.394</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R22C38[0][A]</td>
<td>led/r_cnt_13_s0/CLK</td>
</tr>
<tr>
<td>1.071</td>
<td>0.001</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R22C38[0][A]</td>
<td>led/r_cnt_13_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.675, 63.157%; route: 0.394, 36.843%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.191, 51.000%; route: 0.008, 2.000%; tC2Q: 0.176, 47.000%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.675, 63.157%; route: 0.394, 36.843%</td>
</tr>
</table>
<h3>Path2</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.374</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.452</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.078</td>
</tr>
<tr>
<td class="label">From</td>
<td>led/r_cnt_25_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>led/r_cnt_25_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>i_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>i_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>i_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>i_clk_ibuf/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>204</td>
<td>IOB12[A]</td>
<td>i_clk_ibuf/O</td>
</tr>
<tr>
<td>1.077</td>
<td>0.401</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C37[0][A]</td>
<td>led/r_cnt_25_s0/CLK</td>
</tr>
<tr>
<td>1.253</td>
<td>0.176</td>
<td>tC2Q</td>
<td>RF</td>
<td>3</td>
<td>R21C37[0][A]</td>
<td style=" font-weight:bold;">led/r_cnt_25_s0/Q</td>
</tr>
<tr>
<td>1.261</td>
<td>0.008</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R21C37[0][A]</td>
<td>led/n73_s2/I1</td>
</tr>
<tr>
<td>1.452</td>
<td>0.191</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R21C37[0][A]</td>
<td style=" background: #97FFFF;">led/n73_s2/F</td>
</tr>
<tr>
<td>1.452</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R21C37[0][A]</td>
<td style=" font-weight:bold;">led/r_cnt_25_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>i_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>i_clk_ibuf/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>204</td>
<td>IOB12[A]</td>
<td>i_clk_ibuf/O</td>
</tr>
<tr>
<td>1.077</td>
<td>0.401</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C37[0][A]</td>
<td>led/r_cnt_25_s0/CLK</td>
</tr>
<tr>
<td>1.078</td>
<td>0.001</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R21C37[0][A]</td>
<td>led/r_cnt_25_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.675, 62.735%; route: 0.401, 37.265%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.191, 51.000%; route: 0.008, 2.000%; tC2Q: 0.176, 47.000%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.675, 62.735%; route: 0.401, 37.265%</td>
</tr>
</table>
<h3>Path3</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.374</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.420</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.046</td>
</tr>
<tr>
<td class="label">From</td>
<td>digitaltube/ro_sel_s2</td>
</tr>
<tr>
<td class="label">To</td>
<td>digitaltube/ro_sel_s2</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>i_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>i_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>i_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>i_clk_ibuf/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>204</td>
<td>IOB12[A]</td>
<td>i_clk_ibuf/O</td>
</tr>
<tr>
<td>1.045</td>
<td>0.369</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C32[1][A]</td>
<td>digitaltube/ro_sel_s2/CLK</td>
</tr>
<tr>
<td>1.221</td>
<td>0.176</td>
<td>tC2Q</td>
<td>RF</td>
<td>9</td>
<td>R17C32[1][A]</td>
<td style=" font-weight:bold;">digitaltube/ro_sel_s2/Q</td>
</tr>
<tr>
<td>1.229</td>
<td>0.008</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R17C32[1][A]</td>
<td>digitaltube/n114_s3/I0</td>
</tr>
<tr>
<td>1.420</td>
<td>0.191</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R17C32[1][A]</td>
<td style=" background: #97FFFF;">digitaltube/n114_s3/F</td>
</tr>
<tr>
<td>1.420</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R17C32[1][A]</td>
<td style=" font-weight:bold;">digitaltube/ro_sel_s2/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>i_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>i_clk_ibuf/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>204</td>
<td>IOB12[A]</td>
<td>i_clk_ibuf/O</td>
</tr>
<tr>
<td>1.045</td>
<td>0.369</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C32[1][A]</td>
<td>digitaltube/ro_sel_s2/CLK</td>
</tr>
<tr>
<td>1.046</td>
<td>0.001</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R17C32[1][A]</td>
<td>digitaltube/ro_sel_s2</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.675, 64.649%; route: 0.369, 35.351%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.191, 51.000%; route: 0.008, 2.000%; tC2Q: 0.176, 47.000%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.675, 64.649%; route: 0.369, 35.351%</td>
</tr>
</table>
<h3>Path4</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.374</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.447</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.073</td>
</tr>
<tr>
<td class="label">From</td>
<td>digitaltube/r_cnt_6_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>digitaltube/r_cnt_6_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>i_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>i_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>i_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>i_clk_ibuf/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>204</td>
<td>IOB12[A]</td>
<td>i_clk_ibuf/O</td>
</tr>
<tr>
<td>1.072</td>
<td>0.396</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C34[0][A]</td>
<td>digitaltube/r_cnt_6_s0/CLK</td>
</tr>
<tr>
<td>1.248</td>
<td>0.176</td>
<td>tC2Q</td>
<td>RF</td>
<td>4</td>
<td>R21C34[0][A]</td>
<td style=" font-weight:bold;">digitaltube/r_cnt_6_s0/Q</td>
</tr>
<tr>
<td>1.255</td>
<td>0.008</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R21C34[0][A]</td>
<td>digitaltube/n72_s2/I3</td>
</tr>
<tr>
<td>1.447</td>
<td>0.191</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R21C34[0][A]</td>
<td style=" background: #97FFFF;">digitaltube/n72_s2/F</td>
</tr>
<tr>
<td>1.447</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R21C34[0][A]</td>
<td style=" font-weight:bold;">digitaltube/r_cnt_6_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>i_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>i_clk_ibuf/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>204</td>
<td>IOB12[A]</td>
<td>i_clk_ibuf/O</td>
</tr>
<tr>
<td>1.072</td>
<td>0.396</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C34[0][A]</td>
<td>digitaltube/r_cnt_6_s0/CLK</td>
</tr>
<tr>
<td>1.073</td>
<td>0.001</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R21C34[0][A]</td>
<td>digitaltube/r_cnt_6_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.675, 63.028%; route: 0.396, 36.972%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.191, 51.000%; route: 0.008, 2.000%; tC2Q: 0.176, 47.000%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.675, 63.028%; route: 0.396, 36.972%</td>
</tr>
</table>
<h3>Path5</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.374</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.450</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.076</td>
</tr>
<tr>
<td class="label">From</td>
<td>digitaltube/r_cnt_9_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>digitaltube/r_cnt_9_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>i_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>i_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>i_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>i_clk_ibuf/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>204</td>
<td>IOB12[A]</td>
<td>i_clk_ibuf/O</td>
</tr>
<tr>
<td>1.075</td>
<td>0.399</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R22C33[1][A]</td>
<td>digitaltube/r_cnt_9_s0/CLK</td>
</tr>
<tr>
<td>1.251</td>
<td>0.176</td>
<td>tC2Q</td>
<td>RF</td>
<td>5</td>
<td>R22C33[1][A]</td>
<td style=" font-weight:bold;">digitaltube/r_cnt_9_s0/Q</td>
</tr>
<tr>
<td>1.258</td>
<td>0.008</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R22C33[1][A]</td>
<td>digitaltube/n69_s2/I1</td>
</tr>
<tr>
<td>1.450</td>
<td>0.191</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R22C33[1][A]</td>
<td style=" background: #97FFFF;">digitaltube/n69_s2/F</td>
</tr>
<tr>
<td>1.450</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R22C33[1][A]</td>
<td style=" font-weight:bold;">digitaltube/r_cnt_9_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>i_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>i_clk_ibuf/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>204</td>
<td>IOB12[A]</td>
<td>i_clk_ibuf/O</td>
</tr>
<tr>
<td>1.075</td>
<td>0.399</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R22C33[1][A]</td>
<td>digitaltube/r_cnt_9_s0/CLK</td>
</tr>
<tr>
<td>1.076</td>
<td>0.001</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R22C33[1][A]</td>
<td>digitaltube/r_cnt_9_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.675, 62.863%; route: 0.399, 37.137%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.191, 51.000%; route: 0.008, 2.000%; tC2Q: 0.176, 47.000%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.675, 62.863%; route: 0.399, 37.137%</td>
</tr>
</table>
<h3>Path6</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.374</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.450</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.076</td>
</tr>
<tr>
<td class="label">From</td>
<td>digitaltube/r_cnt_10_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>digitaltube/r_cnt_10_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>i_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>i_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>i_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>i_clk_ibuf/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>204</td>
<td>IOB12[A]</td>
<td>i_clk_ibuf/O</td>
</tr>
<tr>
<td>1.075</td>
<td>0.399</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R22C33[0][A]</td>
<td>digitaltube/r_cnt_10_s0/CLK</td>
</tr>
<tr>
<td>1.251</td>
<td>0.176</td>
<td>tC2Q</td>
<td>RF</td>
<td>4</td>
<td>R22C33[0][A]</td>
<td style=" font-weight:bold;">digitaltube/r_cnt_10_s0/Q</td>
</tr>
<tr>
<td>1.258</td>
<td>0.008</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R22C33[0][A]</td>
<td>digitaltube/n68_s2/I2</td>
</tr>
<tr>
<td>1.450</td>
<td>0.191</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R22C33[0][A]</td>
<td style=" background: #97FFFF;">digitaltube/n68_s2/F</td>
</tr>
<tr>
<td>1.450</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R22C33[0][A]</td>
<td style=" font-weight:bold;">digitaltube/r_cnt_10_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>i_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>i_clk_ibuf/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>204</td>
<td>IOB12[A]</td>
<td>i_clk_ibuf/O</td>
</tr>
<tr>
<td>1.075</td>
<td>0.399</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R22C33[0][A]</td>
<td>digitaltube/r_cnt_10_s0/CLK</td>
</tr>
<tr>
<td>1.076</td>
<td>0.001</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R22C33[0][A]</td>
<td>digitaltube/r_cnt_10_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.675, 62.863%; route: 0.399, 37.137%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.191, 51.000%; route: 0.008, 2.000%; tC2Q: 0.176, 47.000%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.675, 62.863%; route: 0.399, 37.137%</td>
</tr>
</table>
<h3>Path7</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.374</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.442</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.068</td>
</tr>
<tr>
<td class="label">From</td>
<td>digitaltube/r_cnt_13_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>digitaltube/r_cnt_13_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>i_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>i_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>i_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>i_clk_ibuf/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>204</td>
<td>IOB12[A]</td>
<td>i_clk_ibuf/O</td>
</tr>
<tr>
<td>1.067</td>
<td>0.391</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C31[0][A]</td>
<td>digitaltube/r_cnt_13_s0/CLK</td>
</tr>
<tr>
<td>1.243</td>
<td>0.176</td>
<td>tC2Q</td>
<td>RF</td>
<td>5</td>
<td>R21C31[0][A]</td>
<td style=" font-weight:bold;">digitaltube/r_cnt_13_s0/Q</td>
</tr>
<tr>
<td>1.251</td>
<td>0.008</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R21C31[0][A]</td>
<td>digitaltube/n65_s2/I0</td>
</tr>
<tr>
<td>1.442</td>
<td>0.191</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R21C31[0][A]</td>
<td style=" background: #97FFFF;">digitaltube/n65_s2/F</td>
</tr>
<tr>
<td>1.442</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R21C31[0][A]</td>
<td style=" font-weight:bold;">digitaltube/r_cnt_13_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>i_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>i_clk_ibuf/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>204</td>
<td>IOB12[A]</td>
<td>i_clk_ibuf/O</td>
</tr>
<tr>
<td>1.067</td>
<td>0.391</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C31[0][A]</td>
<td>digitaltube/r_cnt_13_s0/CLK</td>
</tr>
<tr>
<td>1.068</td>
<td>0.001</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R21C31[0][A]</td>
<td>digitaltube/r_cnt_13_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.675, 63.323%; route: 0.391, 36.677%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.191, 51.000%; route: 0.008, 2.000%; tC2Q: 0.176, 47.000%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.675, 63.323%; route: 0.391, 36.677%</td>
</tr>
</table>
<h3>Path8</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.374</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.445</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.071</td>
</tr>
<tr>
<td class="label">From</td>
<td>digitaltube/r_cnt_14_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>digitaltube/r_cnt_14_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>i_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>i_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>i_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>i_clk_ibuf/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>204</td>
<td>IOB12[A]</td>
<td>i_clk_ibuf/O</td>
</tr>
<tr>
<td>1.070</td>
<td>0.394</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R22C32[0][A]</td>
<td>digitaltube/r_cnt_14_s0/CLK</td>
</tr>
<tr>
<td>1.246</td>
<td>0.176</td>
<td>tC2Q</td>
<td>RF</td>
<td>4</td>
<td>R22C32[0][A]</td>
<td style=" font-weight:bold;">digitaltube/r_cnt_14_s0/Q</td>
</tr>
<tr>
<td>1.253</td>
<td>0.008</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R22C32[0][A]</td>
<td>digitaltube/n64_s2/I2</td>
</tr>
<tr>
<td>1.445</td>
<td>0.191</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R22C32[0][A]</td>
<td style=" background: #97FFFF;">digitaltube/n64_s2/F</td>
</tr>
<tr>
<td>1.445</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R22C32[0][A]</td>
<td style=" font-weight:bold;">digitaltube/r_cnt_14_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>i_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>i_clk_ibuf/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>204</td>
<td>IOB12[A]</td>
<td>i_clk_ibuf/O</td>
</tr>
<tr>
<td>1.070</td>
<td>0.394</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R22C32[0][A]</td>
<td>digitaltube/r_cnt_14_s0/CLK</td>
</tr>
<tr>
<td>1.071</td>
<td>0.001</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R22C32[0][A]</td>
<td>digitaltube/r_cnt_14_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.675, 63.157%; route: 0.394, 36.843%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.191, 51.000%; route: 0.008, 2.000%; tC2Q: 0.176, 47.000%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.675, 63.157%; route: 0.394, 36.843%</td>
</tr>
</table>
<h3>Path9</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.374</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.445</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.071</td>
</tr>
<tr>
<td class="label">From</td>
<td>digitaltube/r_cnt_18_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>digitaltube/r_cnt_18_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>i_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>i_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>i_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>i_clk_ibuf/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>204</td>
<td>IOB12[A]</td>
<td>i_clk_ibuf/O</td>
</tr>
<tr>
<td>1.070</td>
<td>0.394</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R22C32[1][A]</td>
<td>digitaltube/r_cnt_18_s0/CLK</td>
</tr>
<tr>
<td>1.246</td>
<td>0.176</td>
<td>tC2Q</td>
<td>RF</td>
<td>5</td>
<td>R22C32[1][A]</td>
<td style=" font-weight:bold;">digitaltube/r_cnt_18_s0/Q</td>
</tr>
<tr>
<td>1.253</td>
<td>0.008</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R22C32[1][A]</td>
<td>digitaltube/n60_s2/I1</td>
</tr>
<tr>
<td>1.445</td>
<td>0.191</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R22C32[1][A]</td>
<td style=" background: #97FFFF;">digitaltube/n60_s2/F</td>
</tr>
<tr>
<td>1.445</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R22C32[1][A]</td>
<td style=" font-weight:bold;">digitaltube/r_cnt_18_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>i_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>i_clk_ibuf/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>204</td>
<td>IOB12[A]</td>
<td>i_clk_ibuf/O</td>
</tr>
<tr>
<td>1.070</td>
<td>0.394</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R22C32[1][A]</td>
<td>digitaltube/r_cnt_18_s0/CLK</td>
</tr>
<tr>
<td>1.071</td>
<td>0.001</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R22C32[1][A]</td>
<td>digitaltube/r_cnt_18_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.675, 63.157%; route: 0.394, 36.843%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.191, 51.000%; route: 0.008, 2.000%; tC2Q: 0.176, 47.000%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.675, 63.157%; route: 0.394, 36.843%</td>
</tr>
</table>
<h3>Path10</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.374</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.426</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.053</td>
</tr>
<tr>
<td class="label">From</td>
<td>button3/r_cnt_2_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>button3/r_cnt_2_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>i_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>i_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>i_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>i_clk_ibuf/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>204</td>
<td>IOB12[A]</td>
<td>i_clk_ibuf/O</td>
</tr>
<tr>
<td>1.051</td>
<td>0.376</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C41[1][A]</td>
<td>button3/r_cnt_2_s0/CLK</td>
</tr>
<tr>
<td>1.228</td>
<td>0.176</td>
<td>tC2Q</td>
<td>RF</td>
<td>3</td>
<td>R18C41[1][A]</td>
<td style=" font-weight:bold;">button3/r_cnt_2_s0/Q</td>
</tr>
<tr>
<td>1.235</td>
<td>0.008</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C41[1][A]</td>
<td>button3/n91_s4/I1</td>
</tr>
<tr>
<td>1.426</td>
<td>0.191</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R18C41[1][A]</td>
<td style=" background: #97FFFF;">button3/n91_s4/F</td>
</tr>
<tr>
<td>1.426</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C41[1][A]</td>
<td style=" font-weight:bold;">button3/r_cnt_2_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>i_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>i_clk_ibuf/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>204</td>
<td>IOB12[A]</td>
<td>i_clk_ibuf/O</td>
</tr>
<tr>
<td>1.051</td>
<td>0.376</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C41[1][A]</td>
<td>button3/r_cnt_2_s0/CLK</td>
</tr>
<tr>
<td>1.053</td>
<td>0.001</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R18C41[1][A]</td>
<td>button3/r_cnt_2_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.675, 64.245%; route: 0.376, 35.755%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.191, 51.000%; route: 0.008, 2.000%; tC2Q: 0.176, 47.000%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.675, 64.245%; route: 0.376, 35.755%</td>
</tr>
</table>
<h3>Path11</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.374</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.449</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.075</td>
</tr>
<tr>
<td class="label">From</td>
<td>button3/r_cnt_3_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>button3/r_cnt_3_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>i_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>i_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>i_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>i_clk_ibuf/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>204</td>
<td>IOB12[A]</td>
<td>i_clk_ibuf/O</td>
</tr>
<tr>
<td>1.074</td>
<td>0.398</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C40[1][A]</td>
<td>button3/r_cnt_3_s0/CLK</td>
</tr>
<tr>
<td>1.250</td>
<td>0.176</td>
<td>tC2Q</td>
<td>RF</td>
<td>2</td>
<td>R20C40[1][A]</td>
<td style=" font-weight:bold;">button3/r_cnt_3_s0/Q</td>
</tr>
<tr>
<td>1.258</td>
<td>0.008</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R20C40[1][A]</td>
<td>button3/n90_s2/I3</td>
</tr>
<tr>
<td>1.449</td>
<td>0.191</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R20C40[1][A]</td>
<td style=" background: #97FFFF;">button3/n90_s2/F</td>
</tr>
<tr>
<td>1.449</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R20C40[1][A]</td>
<td style=" font-weight:bold;">button3/r_cnt_3_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>i_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>i_clk_ibuf/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>204</td>
<td>IOB12[A]</td>
<td>i_clk_ibuf/O</td>
</tr>
<tr>
<td>1.074</td>
<td>0.398</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C40[1][A]</td>
<td>button3/r_cnt_3_s0/CLK</td>
</tr>
<tr>
<td>1.075</td>
<td>0.001</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R20C40[1][A]</td>
<td>button3/r_cnt_3_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.675, 62.899%; route: 0.398, 37.101%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.191, 51.000%; route: 0.008, 2.000%; tC2Q: 0.176, 47.000%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.675, 62.899%; route: 0.398, 37.101%</td>
</tr>
</table>
<h3>Path12</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.374</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.426</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.053</td>
</tr>
<tr>
<td class="label">From</td>
<td>button3/r_cnt_5_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>button3/r_cnt_5_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>i_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>i_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>i_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>i_clk_ibuf/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>204</td>
<td>IOB12[A]</td>
<td>i_clk_ibuf/O</td>
</tr>
<tr>
<td>1.051</td>
<td>0.376</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C41[0][A]</td>
<td>button3/r_cnt_5_s0/CLK</td>
</tr>
<tr>
<td>1.228</td>
<td>0.176</td>
<td>tC2Q</td>
<td>RF</td>
<td>3</td>
<td>R18C41[0][A]</td>
<td style=" font-weight:bold;">button3/r_cnt_5_s0/Q</td>
</tr>
<tr>
<td>1.235</td>
<td>0.008</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C41[0][A]</td>
<td>button3/n88_s2/I3</td>
</tr>
<tr>
<td>1.426</td>
<td>0.191</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R18C41[0][A]</td>
<td style=" background: #97FFFF;">button3/n88_s2/F</td>
</tr>
<tr>
<td>1.426</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C41[0][A]</td>
<td style=" font-weight:bold;">button3/r_cnt_5_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>i_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>i_clk_ibuf/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>204</td>
<td>IOB12[A]</td>
<td>i_clk_ibuf/O</td>
</tr>
<tr>
<td>1.051</td>
<td>0.376</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C41[0][A]</td>
<td>button3/r_cnt_5_s0/CLK</td>
</tr>
<tr>
<td>1.053</td>
<td>0.001</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R18C41[0][A]</td>
<td>button3/r_cnt_5_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.675, 64.245%; route: 0.376, 35.755%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.191, 51.000%; route: 0.008, 2.000%; tC2Q: 0.176, 47.000%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.675, 64.245%; route: 0.376, 35.755%</td>
</tr>
</table>
<h3>Path13</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.374</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.417</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.043</td>
</tr>
<tr>
<td class="label">From</td>
<td>button2/r_cnt_23_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>button2/r_cnt_23_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>i_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>i_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>i_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>i_clk_ibuf/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>204</td>
<td>IOB12[A]</td>
<td>i_clk_ibuf/O</td>
</tr>
<tr>
<td>1.042</td>
<td>0.366</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R15C34[0][A]</td>
<td>button2/r_cnt_23_s0/CLK</td>
</tr>
<tr>
<td>1.218</td>
<td>0.176</td>
<td>tC2Q</td>
<td>RF</td>
<td>2</td>
<td>R15C34[0][A]</td>
<td style=" font-weight:bold;">button2/r_cnt_23_s0/Q</td>
</tr>
<tr>
<td>1.225</td>
<td>0.008</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R15C34[0][A]</td>
<td>button2/n70_s2/I3</td>
</tr>
<tr>
<td>1.417</td>
<td>0.191</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R15C34[0][A]</td>
<td style=" background: #97FFFF;">button2/n70_s2/F</td>
</tr>
<tr>
<td>1.417</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R15C34[0][A]</td>
<td style=" font-weight:bold;">button2/r_cnt_23_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>i_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>i_clk_ibuf/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>204</td>
<td>IOB12[A]</td>
<td>i_clk_ibuf/O</td>
</tr>
<tr>
<td>1.042</td>
<td>0.366</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R15C34[0][A]</td>
<td>button2/r_cnt_23_s0/CLK</td>
</tr>
<tr>
<td>1.043</td>
<td>0.001</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R15C34[0][A]</td>
<td>button2/r_cnt_23_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.675, 64.843%; route: 0.366, 35.157%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.191, 51.000%; route: 0.008, 2.000%; tC2Q: 0.176, 47.000%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.675, 64.843%; route: 0.366, 35.157%</td>
</tr>
</table>
<h3>Path14</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.374</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.412</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.038</td>
</tr>
<tr>
<td class="label">From</td>
<td>button2/r_cnt_2_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>button2/r_cnt_2_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>i_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>i_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>i_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>i_clk_ibuf/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>204</td>
<td>IOB12[A]</td>
<td>i_clk_ibuf/O</td>
</tr>
<tr>
<td>1.037</td>
<td>0.361</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R14C34[0][A]</td>
<td>button2/r_cnt_2_s0/CLK</td>
</tr>
<tr>
<td>1.213</td>
<td>0.176</td>
<td>tC2Q</td>
<td>RF</td>
<td>3</td>
<td>R14C34[0][A]</td>
<td style=" font-weight:bold;">button2/r_cnt_2_s0/Q</td>
</tr>
<tr>
<td>1.220</td>
<td>0.008</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R14C34[0][A]</td>
<td>button2/n91_s4/I1</td>
</tr>
<tr>
<td>1.412</td>
<td>0.191</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R14C34[0][A]</td>
<td style=" background: #97FFFF;">button2/n91_s4/F</td>
</tr>
<tr>
<td>1.412</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R14C34[0][A]</td>
<td style=" font-weight:bold;">button2/r_cnt_2_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>i_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>i_clk_ibuf/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>204</td>
<td>IOB12[A]</td>
<td>i_clk_ibuf/O</td>
</tr>
<tr>
<td>1.037</td>
<td>0.361</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R14C34[0][A]</td>
<td>button2/r_cnt_2_s0/CLK</td>
</tr>
<tr>
<td>1.038</td>
<td>0.001</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R14C34[0][A]</td>
<td>button2/r_cnt_2_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.675, 65.156%; route: 0.361, 34.844%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.191, 51.000%; route: 0.008, 2.000%; tC2Q: 0.176, 47.000%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.675, 65.156%; route: 0.361, 34.844%</td>
</tr>
</table>
<h3>Path15</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.374</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.422</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.048</td>
</tr>
<tr>
<td class="label">From</td>
<td>button2/r_cnt_5_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>button2/r_cnt_5_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>i_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>i_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>i_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>i_clk_ibuf/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>204</td>
<td>IOB12[A]</td>
<td>i_clk_ibuf/O</td>
</tr>
<tr>
<td>1.047</td>
<td>0.371</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R15C33[1][A]</td>
<td>button2/r_cnt_5_s0/CLK</td>
</tr>
<tr>
<td>1.223</td>
<td>0.176</td>
<td>tC2Q</td>
<td>RF</td>
<td>3</td>
<td>R15C33[1][A]</td>
<td style=" font-weight:bold;">button2/r_cnt_5_s0/Q</td>
</tr>
<tr>
<td>1.231</td>
<td>0.008</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R15C33[1][A]</td>
<td>button2/n88_s2/I3</td>
</tr>
<tr>
<td>1.422</td>
<td>0.191</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R15C33[1][A]</td>
<td style=" background: #97FFFF;">button2/n88_s2/F</td>
</tr>
<tr>
<td>1.422</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R15C33[1][A]</td>
<td style=" font-weight:bold;">button2/r_cnt_5_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>i_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>i_clk_ibuf/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>204</td>
<td>IOB12[A]</td>
<td>i_clk_ibuf/O</td>
</tr>
<tr>
<td>1.047</td>
<td>0.371</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R15C33[1][A]</td>
<td>button2/r_cnt_5_s0/CLK</td>
</tr>
<tr>
<td>1.048</td>
<td>0.001</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R15C33[1][A]</td>
<td>button2/r_cnt_5_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.675, 64.533%; route: 0.371, 35.467%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.191, 51.000%; route: 0.008, 2.000%; tC2Q: 0.176, 47.000%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.675, 64.533%; route: 0.371, 35.467%</td>
</tr>
</table>
<h3>Path16</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.374</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.418</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.045</td>
</tr>
<tr>
<td class="label">From</td>
<td>button2/r_cnt_9_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>button2/r_cnt_9_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>i_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>i_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>i_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>i_clk_ibuf/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>204</td>
<td>IOB12[A]</td>
<td>i_clk_ibuf/O</td>
</tr>
<tr>
<td>1.043</td>
<td>0.368</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R16C32[1][A]</td>
<td>button2/r_cnt_9_s0/CLK</td>
</tr>
<tr>
<td>1.220</td>
<td>0.176</td>
<td>tC2Q</td>
<td>RF</td>
<td>4</td>
<td>R16C32[1][A]</td>
<td style=" font-weight:bold;">button2/r_cnt_9_s0/Q</td>
</tr>
<tr>
<td>1.227</td>
<td>0.008</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R16C32[1][A]</td>
<td>button2/n84_s2/I3</td>
</tr>
<tr>
<td>1.418</td>
<td>0.191</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R16C32[1][A]</td>
<td style=" background: #97FFFF;">button2/n84_s2/F</td>
</tr>
<tr>
<td>1.418</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R16C32[1][A]</td>
<td style=" font-weight:bold;">button2/r_cnt_9_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>i_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>i_clk_ibuf/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>204</td>
<td>IOB12[A]</td>
<td>i_clk_ibuf/O</td>
</tr>
<tr>
<td>1.043</td>
<td>0.368</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R16C32[1][A]</td>
<td>button2/r_cnt_9_s0/CLK</td>
</tr>
<tr>
<td>1.045</td>
<td>0.001</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R16C32[1][A]</td>
<td>button2/r_cnt_9_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.675, 64.746%; route: 0.368, 35.254%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.191, 51.000%; route: 0.008, 2.000%; tC2Q: 0.176, 47.000%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.675, 64.746%; route: 0.368, 35.254%</td>
</tr>
</table>
<h3>Path17</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.374</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.412</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.038</td>
</tr>
<tr>
<td class="label">From</td>
<td>button1/r_cnt_3_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>button1/r_cnt_3_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>i_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>i_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>i_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>i_clk_ibuf/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>204</td>
<td>IOB12[A]</td>
<td>i_clk_ibuf/O</td>
</tr>
<tr>
<td>1.037</td>
<td>0.361</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R15C35[0][A]</td>
<td>button1/r_cnt_3_s0/CLK</td>
</tr>
<tr>
<td>1.213</td>
<td>0.176</td>
<td>tC2Q</td>
<td>RF</td>
<td>2</td>
<td>R15C35[0][A]</td>
<td style=" font-weight:bold;">button1/r_cnt_3_s0/Q</td>
</tr>
<tr>
<td>1.220</td>
<td>0.008</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R15C35[0][A]</td>
<td>button1/n90_s2/I3</td>
</tr>
<tr>
<td>1.412</td>
<td>0.191</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R15C35[0][A]</td>
<td style=" background: #97FFFF;">button1/n90_s2/F</td>
</tr>
<tr>
<td>1.412</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R15C35[0][A]</td>
<td style=" font-weight:bold;">button1/r_cnt_3_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>i_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>i_clk_ibuf/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>204</td>
<td>IOB12[A]</td>
<td>i_clk_ibuf/O</td>
</tr>
<tr>
<td>1.037</td>
<td>0.361</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R15C35[0][A]</td>
<td>button1/r_cnt_3_s0/CLK</td>
</tr>
<tr>
<td>1.038</td>
<td>0.001</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R15C35[0][A]</td>
<td>button1/r_cnt_3_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.675, 65.156%; route: 0.361, 34.844%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.191, 51.000%; route: 0.008, 2.000%; tC2Q: 0.176, 47.000%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.675, 65.156%; route: 0.361, 34.844%</td>
</tr>
</table>
<h3>Path18</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.374</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.423</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.050</td>
</tr>
<tr>
<td class="label">From</td>
<td>button1/r_cnt_6_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>button1/r_cnt_6_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>i_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>i_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>i_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>i_clk_ibuf/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>204</td>
<td>IOB12[A]</td>
<td>i_clk_ibuf/O</td>
</tr>
<tr>
<td>1.048</td>
<td>0.373</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R16C37[0][A]</td>
<td>button1/r_cnt_6_s0/CLK</td>
</tr>
<tr>
<td>1.225</td>
<td>0.176</td>
<td>tC2Q</td>
<td>RF</td>
<td>4</td>
<td>R16C37[0][A]</td>
<td style=" font-weight:bold;">button1/r_cnt_6_s0/Q</td>
</tr>
<tr>
<td>1.232</td>
<td>0.008</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R16C37[0][A]</td>
<td>button1/n87_s2/I1</td>
</tr>
<tr>
<td>1.423</td>
<td>0.191</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R16C37[0][A]</td>
<td style=" background: #97FFFF;">button1/n87_s2/F</td>
</tr>
<tr>
<td>1.423</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R16C37[0][A]</td>
<td style=" font-weight:bold;">button1/r_cnt_6_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>i_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>i_clk_ibuf/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>204</td>
<td>IOB12[A]</td>
<td>i_clk_ibuf/O</td>
</tr>
<tr>
<td>1.048</td>
<td>0.373</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R16C37[0][A]</td>
<td>button1/r_cnt_6_s0/CLK</td>
</tr>
<tr>
<td>1.050</td>
<td>0.001</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R16C37[0][A]</td>
<td>button1/r_cnt_6_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.675, 64.437%; route: 0.373, 35.563%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.191, 51.000%; route: 0.008, 2.000%; tC2Q: 0.176, 47.000%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.675, 64.437%; route: 0.373, 35.563%</td>
</tr>
</table>
<h3>Path19</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.374</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.422</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.048</td>
</tr>
<tr>
<td class="label">From</td>
<td>button1/r_cnt_15_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>button1/r_cnt_15_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>i_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>i_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>i_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>i_clk_ibuf/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>204</td>
<td>IOB12[A]</td>
<td>i_clk_ibuf/O</td>
</tr>
<tr>
<td>1.047</td>
<td>0.371</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R15C37[0][A]</td>
<td>button1/r_cnt_15_s0/CLK</td>
</tr>
<tr>
<td>1.223</td>
<td>0.176</td>
<td>tC2Q</td>
<td>RF</td>
<td>4</td>
<td>R15C37[0][A]</td>
<td style=" font-weight:bold;">button1/r_cnt_15_s0/Q</td>
</tr>
<tr>
<td>1.231</td>
<td>0.008</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R15C37[0][A]</td>
<td>button1/n78_s2/I3</td>
</tr>
<tr>
<td>1.422</td>
<td>0.191</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R15C37[0][A]</td>
<td style=" background: #97FFFF;">button1/n78_s2/F</td>
</tr>
<tr>
<td>1.422</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R15C37[0][A]</td>
<td style=" font-weight:bold;">button1/r_cnt_15_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>i_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>i_clk_ibuf/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>204</td>
<td>IOB12[A]</td>
<td>i_clk_ibuf/O</td>
</tr>
<tr>
<td>1.047</td>
<td>0.371</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R15C37[0][A]</td>
<td>button1/r_cnt_15_s0/CLK</td>
</tr>
<tr>
<td>1.048</td>
<td>0.001</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R15C37[0][A]</td>
<td>button1/r_cnt_15_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.675, 64.533%; route: 0.371, 35.467%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.191, 51.000%; route: 0.008, 2.000%; tC2Q: 0.176, 47.000%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.675, 64.533%; route: 0.371, 35.467%</td>
</tr>
</table>
<h3>Path20</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.374</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.417</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.043</td>
</tr>
<tr>
<td class="label">From</td>
<td>button1/r_cnt_17_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>button1/r_cnt_17_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>i_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>i_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>i_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>i_clk_ibuf/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>204</td>
<td>IOB12[A]</td>
<td>i_clk_ibuf/O</td>
</tr>
<tr>
<td>1.042</td>
<td>0.366</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R15C36[0][A]</td>
<td>button1/r_cnt_17_s0/CLK</td>
</tr>
<tr>
<td>1.218</td>
<td>0.176</td>
<td>tC2Q</td>
<td>RF</td>
<td>6</td>
<td>R15C36[0][A]</td>
<td style=" font-weight:bold;">button1/r_cnt_17_s0/Q</td>
</tr>
<tr>
<td>1.225</td>
<td>0.008</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R15C36[0][A]</td>
<td>button1/n76_s2/I3</td>
</tr>
<tr>
<td>1.417</td>
<td>0.191</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R15C36[0][A]</td>
<td style=" background: #97FFFF;">button1/n76_s2/F</td>
</tr>
<tr>
<td>1.417</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R15C36[0][A]</td>
<td style=" font-weight:bold;">button1/r_cnt_17_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>i_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>i_clk_ibuf/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>204</td>
<td>IOB12[A]</td>
<td>i_clk_ibuf/O</td>
</tr>
<tr>
<td>1.042</td>
<td>0.366</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R15C36[0][A]</td>
<td>button1/r_cnt_17_s0/CLK</td>
</tr>
<tr>
<td>1.043</td>
<td>0.001</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R15C36[0][A]</td>
<td>button1/r_cnt_17_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.675, 64.843%; route: 0.366, 35.157%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.191, 51.000%; route: 0.008, 2.000%; tC2Q: 0.176, 47.000%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.675, 64.843%; route: 0.366, 35.157%</td>
</tr>
</table>
<h3>Path21</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.374</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.407</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.033</td>
</tr>
<tr>
<td class="label">From</td>
<td>button0/r_cnt_2_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>button0/r_cnt_2_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>i_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>i_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>i_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>i_clk_ibuf/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>204</td>
<td>IOB12[A]</td>
<td>i_clk_ibuf/O</td>
</tr>
<tr>
<td>1.032</td>
<td>0.356</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R14C39[1][A]</td>
<td>button0/r_cnt_2_s0/CLK</td>
</tr>
<tr>
<td>1.208</td>
<td>0.176</td>
<td>tC2Q</td>
<td>RF</td>
<td>3</td>
<td>R14C39[1][A]</td>
<td style=" font-weight:bold;">button0/r_cnt_2_s0/Q</td>
</tr>
<tr>
<td>1.215</td>
<td>0.008</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R14C39[1][A]</td>
<td>button0/n91_s3/I1</td>
</tr>
<tr>
<td>1.407</td>
<td>0.191</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R14C39[1][A]</td>
<td style=" background: #97FFFF;">button0/n91_s3/F</td>
</tr>
<tr>
<td>1.407</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R14C39[1][A]</td>
<td style=" font-weight:bold;">button0/r_cnt_2_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>i_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>i_clk_ibuf/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>204</td>
<td>IOB12[A]</td>
<td>i_clk_ibuf/O</td>
</tr>
<tr>
<td>1.032</td>
<td>0.356</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R14C39[1][A]</td>
<td>button0/r_cnt_2_s0/CLK</td>
</tr>
<tr>
<td>1.033</td>
<td>0.001</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R14C39[1][A]</td>
<td>button0/r_cnt_2_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.675, 65.471%; route: 0.356, 34.529%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.191, 51.000%; route: 0.008, 2.000%; tC2Q: 0.176, 47.000%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.675, 65.471%; route: 0.356, 34.529%</td>
</tr>
</table>
<h3>Path22</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.374</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.407</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.033</td>
</tr>
<tr>
<td class="label">From</td>
<td>button0/r_cnt_6_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>button0/r_cnt_6_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>i_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>i_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>i_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>i_clk_ibuf/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>204</td>
<td>IOB12[A]</td>
<td>i_clk_ibuf/O</td>
</tr>
<tr>
<td>1.032</td>
<td>0.356</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R14C39[0][A]</td>
<td>button0/r_cnt_6_s0/CLK</td>
</tr>
<tr>
<td>1.208</td>
<td>0.176</td>
<td>tC2Q</td>
<td>RF</td>
<td>4</td>
<td>R14C39[0][A]</td>
<td style=" font-weight:bold;">button0/r_cnt_6_s0/Q</td>
</tr>
<tr>
<td>1.215</td>
<td>0.008</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R14C39[0][A]</td>
<td>button0/n87_s2/I1</td>
</tr>
<tr>
<td>1.407</td>
<td>0.191</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R14C39[0][A]</td>
<td style=" background: #97FFFF;">button0/n87_s2/F</td>
</tr>
<tr>
<td>1.407</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R14C39[0][A]</td>
<td style=" font-weight:bold;">button0/r_cnt_6_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>i_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>i_clk_ibuf/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>204</td>
<td>IOB12[A]</td>
<td>i_clk_ibuf/O</td>
</tr>
<tr>
<td>1.032</td>
<td>0.356</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R14C39[0][A]</td>
<td>button0/r_cnt_6_s0/CLK</td>
</tr>
<tr>
<td>1.033</td>
<td>0.001</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R14C39[0][A]</td>
<td>button0/r_cnt_6_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.675, 65.471%; route: 0.356, 34.529%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.191, 51.000%; route: 0.008, 2.000%; tC2Q: 0.176, 47.000%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.675, 65.471%; route: 0.356, 34.529%</td>
</tr>
</table>
<h3>Path23</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.374</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.418</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.045</td>
</tr>
<tr>
<td class="label">From</td>
<td>button0/r_cnt_9_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>button0/r_cnt_9_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>i_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>i_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>i_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>i_clk_ibuf/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>204</td>
<td>IOB12[A]</td>
<td>i_clk_ibuf/O</td>
</tr>
<tr>
<td>1.043</td>
<td>0.368</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R16C40[0][A]</td>
<td>button0/r_cnt_9_s0/CLK</td>
</tr>
<tr>
<td>1.220</td>
<td>0.176</td>
<td>tC2Q</td>
<td>RF</td>
<td>4</td>
<td>R16C40[0][A]</td>
<td style=" font-weight:bold;">button0/r_cnt_9_s0/Q</td>
</tr>
<tr>
<td>1.227</td>
<td>0.008</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R16C40[0][A]</td>
<td>button0/n84_s2/I3</td>
</tr>
<tr>
<td>1.418</td>
<td>0.191</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R16C40[0][A]</td>
<td style=" background: #97FFFF;">button0/n84_s2/F</td>
</tr>
<tr>
<td>1.418</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R16C40[0][A]</td>
<td style=" font-weight:bold;">button0/r_cnt_9_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>i_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>i_clk_ibuf/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>204</td>
<td>IOB12[A]</td>
<td>i_clk_ibuf/O</td>
</tr>
<tr>
<td>1.043</td>
<td>0.368</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R16C40[0][A]</td>
<td>button0/r_cnt_9_s0/CLK</td>
</tr>
<tr>
<td>1.045</td>
<td>0.001</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R16C40[0][A]</td>
<td>button0/r_cnt_9_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.675, 64.746%; route: 0.368, 35.254%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.191, 51.000%; route: 0.008, 2.000%; tC2Q: 0.176, 47.000%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.675, 64.746%; route: 0.368, 35.254%</td>
</tr>
</table>
<h3>Path24</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.374</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.422</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.048</td>
</tr>
<tr>
<td class="label">From</td>
<td>button0/r_cnt_13_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>button0/r_cnt_13_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>i_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>i_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>i_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>i_clk_ibuf/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>204</td>
<td>IOB12[A]</td>
<td>i_clk_ibuf/O</td>
</tr>
<tr>
<td>1.047</td>
<td>0.371</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R15C41[0][A]</td>
<td>button0/r_cnt_13_s0/CLK</td>
</tr>
<tr>
<td>1.223</td>
<td>0.176</td>
<td>tC2Q</td>
<td>RF</td>
<td>6</td>
<td>R15C41[0][A]</td>
<td style=" font-weight:bold;">button0/r_cnt_13_s0/Q</td>
</tr>
<tr>
<td>1.231</td>
<td>0.008</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R15C41[0][A]</td>
<td>button0/n80_s2/I1</td>
</tr>
<tr>
<td>1.422</td>
<td>0.191</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R15C41[0][A]</td>
<td style=" background: #97FFFF;">button0/n80_s2/F</td>
</tr>
<tr>
<td>1.422</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R15C41[0][A]</td>
<td style=" font-weight:bold;">button0/r_cnt_13_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>i_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>i_clk_ibuf/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>204</td>
<td>IOB12[A]</td>
<td>i_clk_ibuf/O</td>
</tr>
<tr>
<td>1.047</td>
<td>0.371</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R15C41[0][A]</td>
<td>button0/r_cnt_13_s0/CLK</td>
</tr>
<tr>
<td>1.048</td>
<td>0.001</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R15C41[0][A]</td>
<td>button0/r_cnt_13_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.675, 64.533%; route: 0.371, 35.467%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.191, 51.000%; route: 0.008, 2.000%; tC2Q: 0.176, 47.000%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.675, 64.533%; route: 0.371, 35.467%</td>
</tr>
</table>
<h3>Path25</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.374</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.418</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.045</td>
</tr>
<tr>
<td class="label">From</td>
<td>button0/r_cnt_21_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>button0/r_cnt_21_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>i_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>i_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>i_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>i_clk_ibuf/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>204</td>
<td>IOB12[A]</td>
<td>i_clk_ibuf/O</td>
</tr>
<tr>
<td>1.043</td>
<td>0.368</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R16C38[0][A]</td>
<td>button0/r_cnt_21_s0/CLK</td>
</tr>
<tr>
<td>1.220</td>
<td>0.176</td>
<td>tC2Q</td>
<td>RF</td>
<td>3</td>
<td>R16C38[0][A]</td>
<td style=" font-weight:bold;">button0/r_cnt_21_s0/Q</td>
</tr>
<tr>
<td>1.227</td>
<td>0.008</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R16C38[0][A]</td>
<td>button0/n72_s2/I1</td>
</tr>
<tr>
<td>1.418</td>
<td>0.191</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R16C38[0][A]</td>
<td style=" background: #97FFFF;">button0/n72_s2/F</td>
</tr>
<tr>
<td>1.418</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R16C38[0][A]</td>
<td style=" font-weight:bold;">button0/r_cnt_21_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>i_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>i_clk_ibuf/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>204</td>
<td>IOB12[A]</td>
<td>i_clk_ibuf/O</td>
</tr>
<tr>
<td>1.043</td>
<td>0.368</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R16C38[0][A]</td>
<td>button0/r_cnt_21_s0/CLK</td>
</tr>
<tr>
<td>1.045</td>
<td>0.001</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R16C38[0][A]</td>
<td>button0/r_cnt_21_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.675, 64.746%; route: 0.368, 35.254%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.191, 51.000%; route: 0.008, 2.000%; tC2Q: 0.176, 47.000%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.675, 64.746%; route: 0.368, 35.254%</td>
</tr>
</table>
<h3><a name="Recovery_Analysis">Recovery Analysis Report</a></h3>
<h4>Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1</h4>
<h4>No recovery paths to report!</h4>
<h3><a name="Removal_Analysis">Removal Analysis Report</a></h3>
<h4>Report Command:report_timing -removal -max_paths 25 -max_common_paths 1</h4>
<h4>No removal paths to report!</h4>
<h2><a name="Minimum_Pulse_Width_Report">Minimum Pulse Width Report:</a></h2>
<h4>Report Command:report_min_pulse_width -nworst 10 -detail</h4>
<h3>MPW1</h3>
<p><b>MPW Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack:</td>
<td>4.231</td>
</tr>
<tr>
<td class="label">Actual Width:</td>
<td>4.481</td>
</tr>
<tr>
<td class="label">Required Width:</td>
<td>0.250</td>
</tr>
<tr>
<td class="label">Type:</td>
<td>Low Pulse Width</td>
</tr>
<tr>
<td class="label">Clock:</td>
<td>i_clk</td>
</tr>
<tr>
<td class="label"> Objects:</td>
<td>button3/r_cnt_13_s0</td>
</tr>
</table>
<p><b>Late clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>i_clk</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>i_clk_ibuf/I</td>
</tr>
<tr>
<td>5.688</td>
<td>0.688</td>
<td>tINS</td>
<td>FF</td>
<td>i_clk_ibuf/O</td>
</tr>
<tr>
<td>6.598</td>
<td>0.910</td>
<td>tNET</td>
<td>FF</td>
<td>button3/r_cnt_13_s0/CLK</td>
</tr>
</table>
<p><b>Early clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>i_clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>i_clk_ibuf/I</td>
</tr>
<tr>
<td>10.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>i_clk_ibuf/O</td>
</tr>
<tr>
<td>11.079</td>
<td>0.403</td>
<td>tNET</td>
<td>RR</td>
<td>button3/r_cnt_13_s0/CLK</td>
</tr>
</table>
<h3>MPW2</h3>
<p><b>MPW Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack:</td>
<td>4.231</td>
</tr>
<tr>
<td class="label">Actual Width:</td>
<td>4.481</td>
</tr>
<tr>
<td class="label">Required Width:</td>
<td>0.250</td>
</tr>
<tr>
<td class="label">Type:</td>
<td>Low Pulse Width</td>
</tr>
<tr>
<td class="label">Clock:</td>
<td>i_clk</td>
</tr>
<tr>
<td class="label"> Objects:</td>
<td>digitaltube/r_cnt_11_s0</td>
</tr>
</table>
<p><b>Late clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>i_clk</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>i_clk_ibuf/I</td>
</tr>
<tr>
<td>5.688</td>
<td>0.688</td>
<td>tINS</td>
<td>FF</td>
<td>i_clk_ibuf/O</td>
</tr>
<tr>
<td>6.598</td>
<td>0.910</td>
<td>tNET</td>
<td>FF</td>
<td>digitaltube/r_cnt_11_s0/CLK</td>
</tr>
</table>
<p><b>Early clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>i_clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>i_clk_ibuf/I</td>
</tr>
<tr>
<td>10.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>i_clk_ibuf/O</td>
</tr>
<tr>
<td>11.079</td>
<td>0.403</td>
<td>tNET</td>
<td>RR</td>
<td>digitaltube/r_cnt_11_s0/CLK</td>
</tr>
</table>
<h3>MPW3</h3>
<p><b>MPW Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack:</td>
<td>4.231</td>
</tr>
<tr>
<td class="label">Actual Width:</td>
<td>4.481</td>
</tr>
<tr>
<td class="label">Required Width:</td>
<td>0.250</td>
</tr>
<tr>
<td class="label">Type:</td>
<td>Low Pulse Width</td>
</tr>
<tr>
<td class="label">Clock:</td>
<td>i_clk</td>
</tr>
<tr>
<td class="label"> Objects:</td>
<td>digitaltube/r_cnt_0_s0</td>
</tr>
</table>
<p><b>Late clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>i_clk</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>i_clk_ibuf/I</td>
</tr>
<tr>
<td>5.688</td>
<td>0.688</td>
<td>tINS</td>
<td>FF</td>
<td>i_clk_ibuf/O</td>
</tr>
<tr>
<td>6.598</td>
<td>0.910</td>
<td>tNET</td>
<td>FF</td>
<td>digitaltube/r_cnt_0_s0/CLK</td>
</tr>
</table>
<p><b>Early clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>i_clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>i_clk_ibuf/I</td>
</tr>
<tr>
<td>10.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>i_clk_ibuf/O</td>
</tr>
<tr>
<td>11.079</td>
<td>0.403</td>
<td>tNET</td>
<td>RR</td>
<td>digitaltube/r_cnt_0_s0/CLK</td>
</tr>
</table>
<h3>MPW4</h3>
<p><b>MPW Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack:</td>
<td>4.231</td>
</tr>
<tr>
<td class="label">Actual Width:</td>
<td>4.481</td>
</tr>
<tr>
<td class="label">Required Width:</td>
<td>0.250</td>
</tr>
<tr>
<td class="label">Type:</td>
<td>Low Pulse Width</td>
</tr>
<tr>
<td class="label">Clock:</td>
<td>i_clk</td>
</tr>
<tr>
<td class="label"> Objects:</td>
<td>led/r_cnt_21_s0</td>
</tr>
</table>
<p><b>Late clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>i_clk</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>i_clk_ibuf/I</td>
</tr>
<tr>
<td>5.688</td>
<td>0.688</td>
<td>tINS</td>
<td>FF</td>
<td>i_clk_ibuf/O</td>
</tr>
<tr>
<td>6.598</td>
<td>0.910</td>
<td>tNET</td>
<td>FF</td>
<td>led/r_cnt_21_s0/CLK</td>
</tr>
</table>
<p><b>Early clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>i_clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>i_clk_ibuf/I</td>
</tr>
<tr>
<td>10.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>i_clk_ibuf/O</td>
</tr>
<tr>
<td>11.079</td>
<td>0.403</td>
<td>tNET</td>
<td>RR</td>
<td>led/r_cnt_21_s0/CLK</td>
</tr>
</table>
<h3>MPW5</h3>
<p><b>MPW Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack:</td>
<td>4.231</td>
</tr>
<tr>
<td class="label">Actual Width:</td>
<td>4.481</td>
</tr>
<tr>
<td class="label">Required Width:</td>
<td>0.250</td>
</tr>
<tr>
<td class="label">Type:</td>
<td>Low Pulse Width</td>
</tr>
<tr>
<td class="label">Clock:</td>
<td>i_clk</td>
</tr>
<tr>
<td class="label"> Objects:</td>
<td>led/r_cnt_19_s0</td>
</tr>
</table>
<p><b>Late clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>i_clk</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>i_clk_ibuf/I</td>
</tr>
<tr>
<td>5.688</td>
<td>0.688</td>
<td>tINS</td>
<td>FF</td>
<td>i_clk_ibuf/O</td>
</tr>
<tr>
<td>6.598</td>
<td>0.910</td>
<td>tNET</td>
<td>FF</td>
<td>led/r_cnt_19_s0/CLK</td>
</tr>
</table>
<p><b>Early clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>i_clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>i_clk_ibuf/I</td>
</tr>
<tr>
<td>10.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>i_clk_ibuf/O</td>
</tr>
<tr>
<td>11.079</td>
<td>0.403</td>
<td>tNET</td>
<td>RR</td>
<td>led/r_cnt_19_s0/CLK</td>
</tr>
</table>
<h3>MPW6</h3>
<p><b>MPW Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack:</td>
<td>4.232</td>
</tr>
<tr>
<td class="label">Actual Width:</td>
<td>4.482</td>
</tr>
<tr>
<td class="label">Required Width:</td>
<td>0.250</td>
</tr>
<tr>
<td class="label">Type:</td>
<td>Low Pulse Width</td>
</tr>
<tr>
<td class="label">Clock:</td>
<td>i_clk</td>
</tr>
<tr>
<td class="label"> Objects:</td>
<td>digitaltube/r_cnt_19_s0</td>
</tr>
</table>
<p><b>Late clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>i_clk</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>i_clk_ibuf/I</td>
</tr>
<tr>
<td>5.688</td>
<td>0.688</td>
<td>tINS</td>
<td>FF</td>
<td>i_clk_ibuf/O</td>
</tr>
<tr>
<td>6.595</td>
<td>0.907</td>
<td>tNET</td>
<td>FF</td>
<td>digitaltube/r_cnt_19_s0/CLK</td>
</tr>
</table>
<p><b>Early clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>i_clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>i_clk_ibuf/I</td>
</tr>
<tr>
<td>10.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>i_clk_ibuf/O</td>
</tr>
<tr>
<td>11.077</td>
<td>0.401</td>
<td>tNET</td>
<td>RR</td>
<td>digitaltube/r_cnt_19_s0/CLK</td>
</tr>
</table>
<h3>MPW7</h3>
<p><b>MPW Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack:</td>
<td>4.232</td>
</tr>
<tr>
<td class="label">Actual Width:</td>
<td>4.482</td>
</tr>
<tr>
<td class="label">Required Width:</td>
<td>0.250</td>
</tr>
<tr>
<td class="label">Type:</td>
<td>Low Pulse Width</td>
</tr>
<tr>
<td class="label">Clock:</td>
<td>i_clk</td>
</tr>
<tr>
<td class="label"> Objects:</td>
<td>digitaltube/r_cnt_17_s0</td>
</tr>
</table>
<p><b>Late clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>i_clk</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>i_clk_ibuf/I</td>
</tr>
<tr>
<td>5.688</td>
<td>0.688</td>
<td>tINS</td>
<td>FF</td>
<td>i_clk_ibuf/O</td>
</tr>
<tr>
<td>6.595</td>
<td>0.907</td>
<td>tNET</td>
<td>FF</td>
<td>digitaltube/r_cnt_17_s0/CLK</td>
</tr>
</table>
<p><b>Early clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>i_clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>i_clk_ibuf/I</td>
</tr>
<tr>
<td>10.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>i_clk_ibuf/O</td>
</tr>
<tr>
<td>11.077</td>
<td>0.401</td>
<td>tNET</td>
<td>RR</td>
<td>digitaltube/r_cnt_17_s0/CLK</td>
</tr>
</table>
<h3>MPW8</h3>
<p><b>MPW Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack:</td>
<td>4.232</td>
</tr>
<tr>
<td class="label">Actual Width:</td>
<td>4.482</td>
</tr>
<tr>
<td class="label">Required Width:</td>
<td>0.250</td>
</tr>
<tr>
<td class="label">Type:</td>
<td>Low Pulse Width</td>
</tr>
<tr>
<td class="label">Clock:</td>
<td>i_clk</td>
</tr>
<tr>
<td class="label"> Objects:</td>
<td>digitaltube/r_cnt_12_s0</td>
</tr>
</table>
<p><b>Late clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>i_clk</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>i_clk_ibuf/I</td>
</tr>
<tr>
<td>5.688</td>
<td>0.688</td>
<td>tINS</td>
<td>FF</td>
<td>i_clk_ibuf/O</td>
</tr>
<tr>
<td>6.595</td>
<td>0.907</td>
<td>tNET</td>
<td>FF</td>
<td>digitaltube/r_cnt_12_s0/CLK</td>
</tr>
</table>
<p><b>Early clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>i_clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>i_clk_ibuf/I</td>
</tr>
<tr>
<td>10.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>i_clk_ibuf/O</td>
</tr>
<tr>
<td>11.077</td>
<td>0.401</td>
<td>tNET</td>
<td>RR</td>
<td>digitaltube/r_cnt_12_s0/CLK</td>
</tr>
</table>
<h3>MPW9</h3>
<p><b>MPW Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack:</td>
<td>4.232</td>
</tr>
<tr>
<td class="label">Actual Width:</td>
<td>4.482</td>
</tr>
<tr>
<td class="label">Required Width:</td>
<td>0.250</td>
</tr>
<tr>
<td class="label">Type:</td>
<td>Low Pulse Width</td>
</tr>
<tr>
<td class="label">Clock:</td>
<td>i_clk</td>
</tr>
<tr>
<td class="label"> Objects:</td>
<td>button3/r_cnt_7_s0</td>
</tr>
</table>
<p><b>Late clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>i_clk</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>i_clk_ibuf/I</td>
</tr>
<tr>
<td>5.688</td>
<td>0.688</td>
<td>tINS</td>
<td>FF</td>
<td>i_clk_ibuf/O</td>
</tr>
<tr>
<td>6.595</td>
<td>0.907</td>
<td>tNET</td>
<td>FF</td>
<td>button3/r_cnt_7_s0/CLK</td>
</tr>
</table>
<p><b>Early clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>i_clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>i_clk_ibuf/I</td>
</tr>
<tr>
<td>10.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>i_clk_ibuf/O</td>
</tr>
<tr>
<td>11.077</td>
<td>0.401</td>
<td>tNET</td>
<td>RR</td>
<td>button3/r_cnt_7_s0/CLK</td>
</tr>
</table>
<h3>MPW10</h3>
<p><b>MPW Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack:</td>
<td>4.232</td>
</tr>
<tr>
<td class="label">Actual Width:</td>
<td>4.482</td>
</tr>
<tr>
<td class="label">Required Width:</td>
<td>0.250</td>
</tr>
<tr>
<td class="label">Type:</td>
<td>Low Pulse Width</td>
</tr>
<tr>
<td class="label">Clock:</td>
<td>i_clk</td>
</tr>
<tr>
<td class="label"> Objects:</td>
<td>button3/r_cnt_6_s0</td>
</tr>
</table>
<p><b>Late clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>i_clk</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>i_clk_ibuf/I</td>
</tr>
<tr>
<td>5.688</td>
<td>0.688</td>
<td>tINS</td>
<td>FF</td>
<td>i_clk_ibuf/O</td>
</tr>
<tr>
<td>6.595</td>
<td>0.907</td>
<td>tNET</td>
<td>FF</td>
<td>button3/r_cnt_6_s0/CLK</td>
</tr>
</table>
<p><b>Early clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>i_clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>i_clk_ibuf/I</td>
</tr>
<tr>
<td>10.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>i_clk_ibuf/O</td>
</tr>
<tr>
<td>11.077</td>
<td>0.401</td>
<td>tNET</td>
<td>RR</td>
<td>button3/r_cnt_6_s0/CLK</td>
</tr>
</table>
<h2><a name="High_Fanout_Nets_Report">High Fanout Nets Report:</a></h2>
<h4>Report Command:report_high_fanout_nets -max_nets 10</h4>
<table class="detail_table">
<tr>
<th class="label">FANOUT</th>
<th class="label">NET NAME</th>
<th class="label">WORST SLACK</th>
<th class="label">MAX DELAY</th>
</tr>
<tr>
<td>204</td>
<td>i_clk_d</td>
<td>4.782</td>
<td>0.913</td>
</tr>
<tr>
<td>25</td>
<td>r_cntOnes_4_9</td>
<td>4.894</td>
<td>1.477</td>
</tr>
<tr>
<td>21</td>
<td>n41_3</td>
<td>5.415</td>
<td>0.959</td>
</tr>
<tr>
<td>13</td>
<td>r_cntTens[0]</td>
<td>8.030</td>
<td>0.500</td>
</tr>
<tr>
<td>13</td>
<td>r_cntTens[1]</td>
<td>7.726</td>
<td>0.368</td>
</tr>
<tr>
<td>12</td>
<td>n85_7</td>
<td>5.642</td>
<td>1.446</td>
</tr>
<tr>
<td>11</td>
<td>n75_8</td>
<td>6.750</td>
<td>0.498</td>
</tr>
<tr>
<td>11</td>
<td>n80_7</td>
<td>6.144</td>
<td>0.690</td>
</tr>
<tr>
<td>11</td>
<td>r_cntTens[2]</td>
<td>7.816</td>
<td>0.497</td>
</tr>
<tr>
<td>11</td>
<td>r_cntTens[3]</td>
<td>7.601</td>
<td>0.497</td>
</tr>
</table>
<h2><a name="Route_Congestions_Report">Route Congestions Report:</a></h2>
<h4>Report Command:report_route_congestion -max_grids 10</h4>
<table class="detail_table">
<tr>
<th class="label">GRID LOC</th>
<th class="label">ROUTE CONGESTIONS</th>
</tr>
<tr>
<td>R20C33</td>
<td>37.50%</td>
</tr>
<tr>
<td>R18C33</td>
<td>34.72%</td>
</tr>
<tr>
<td>R17C33</td>
<td>33.33%</td>
</tr>
<tr>
<td>R15C32</td>
<td>31.94%</td>
</tr>
<tr>
<td>R14C40</td>
<td>30.56%</td>
</tr>
<tr>
<td>R18C41</td>
<td>30.56%</td>
</tr>
<tr>
<td>R18C40</td>
<td>29.17%</td>
</tr>
<tr>
<td>R21C33</td>
<td>27.78%</td>
</tr>
<tr>
<td>R18C38</td>
<td>27.78%</td>
</tr>
<tr>
<td>R15C38</td>
<td>26.39%</td>
</tr>
</table>
<h2><a name="Timing_Exceptions_Report">Timing Exceptions Report:</a></h2>
<h3><a name="Setup_Analysis_Exceptions">Setup Analysis Report</a></h3>
<h4>Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1</h4>
<h4>No timing exceptions to report!</h4>
<h3><a name="Hold_Analysis_Exceptions">Hold Analysis Report</a></h3>
<h4>Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1</h4>
<h4>No timing exceptions to report!</h4>
<h3><a name="Recovery_Analysis_Exceptions">Recovery Analysis Report</a></h3>
<h4>Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1</h4>
<h4>No timing exceptions to report!</h4>
<h3><a name="Removal_Analysis_Exceptions">Removal Analysis Report</a></h3>
<h4>Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1</h4>
<h4>No timing exceptions to report!</h4>
<h2><a name="SDC_Report">Timing Constraints Report:</a></h2>
<table class="detail_table">
<tr>
<th class="label">SDC Command Type</th>
<th class="label">State</th>
<th class="label">Detail Command</th>
</tr>
</table>
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